drm/amd/display: Set DISPCLK_MAX_ERRDET_CYCLES to 7

Wesley Chalmers · alexdeucher · commit 3577e1678772 · 2021-06-08T12:23:15.000-04:00
[WHY]
DISPCLK_MAX_ERRDET_CYCLES must be 7 to prevent connection loss when
changing DENTIST_DISPCLK_WDIVIDER from 126 to 127 and back.

Signed-off-by: Wesley Chalmers &lt;Wesley.Chalmers@amd.com&gt;
Reviewed-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Acked-by: Stylon Wang &lt;stylon.wang@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -244,7 +244,7 @@ void dcn20_dccg_init(struct dce_hwseq *hws)
 	REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
 
 	/* This value is dependent on the hardware pipeline delay so set once per SOC */
-	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
+	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
 }
 
 void dcn20_disable_vga(

Original file line number	Diff line number	Diff line change
`@@ -244,7 +244,7 @@ void dcn20_dccg_init(struct dce_hwseq *hws)`
`244`	`244`	`REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);`
`245`	`245`
`246`	`246`	`/* This value is dependent on the hardware pipeline delay so set once per SOC */`
`247`		`- REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);`
	`247`	`+ REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);`
`248`	`248`	`}`
`249`	`249`
`250`	`250`	`void dcn20_disable_vga(`