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ambaruskrzk
ambarus
authored and
krzk
committed
dt-bindings: clock: google,gs101: rename CMU_TOP gate defines
The gs101 clock defines from the bindings header are derived from the clock register names found in the datasheet under some certain rules. The CMU TOP gate clock defines missed to include the required "CMU" differentiator which will cause collisions with the gate clock defines of other clock units. Rename the TOP gate clock defines to include "CMU". Update the clock driver to use the new defines in order to not break compilation and bisect-ability. There are no device trees that use the previous defines. Fixes: 0a910f1 ("dt-bindings: clock: Add Google gs101 clock management unit bindings") Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231218064333.479885-1-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
1 parent 796bb2d commit 35f32e3

2 files changed

Lines changed: 159 additions & 152 deletions

File tree

‎drivers/clk/samsung/clk-gs101.c‎

Lines changed: 87 additions & 80 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
#include "clk-exynos-arm64.h"
1818

1919
/* NOTE: Must be equal to the last clock ID increased by one */
20-
#define CLKS_NR_TOP (CLK_GOUT_TPU_UART + 1)
20+
#define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1)
2121
#define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1)
2222
#define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
2323

@@ -1259,160 +1259,167 @@ static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = {
12591259
};
12601260

12611261
static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {
1262-
GATE(CLK_GOUT_BUS0_BOOST, "gout_cmu_bus0_boost",
1262+
GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost",
12631263
"mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0),
1264-
GATE(CLK_GOUT_BUS1_BOOST, "gout_cmu_bus1_boost",
1264+
GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost",
12651265
"mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS1_BOOST, 21, 0, 0),
1266-
GATE(CLK_GOUT_BUS2_BOOST, "gout_cmu_bus2_boost",
1266+
GATE(CLK_GOUT_CMU_BUS2_BOOST, "gout_cmu_bus2_boost",
12671267
"mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS2_BOOST, 21, 0, 0),
1268-
GATE(CLK_GOUT_CORE_BOOST, "gout_cmu_core_boost",
1268+
GATE(CLK_GOUT_CMU_CORE_BOOST, "gout_cmu_core_boost",
12691269
"mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CORE_BOOST, 21, 0, 0),
1270-
GATE(CLK_GOUT_CPUCL0_BOOST, "gout_cmu_cpucl0_boost",
1270+
GATE(CLK_GOUT_CMU_CPUCL0_BOOST, "gout_cmu_cpucl0_boost",
12711271
"mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,
12721272
21, 0, 0),
1273-
GATE(CLK_GOUT_CPUCL1_BOOST, "gout_cmu_cpucl1_boost",
1273+
GATE(CLK_GOUT_CMU_CPUCL1_BOOST, "gout_cmu_cpucl1_boost",
12741274
"mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,
12751275
21, 0, 0),
1276-
GATE(CLK_GOUT_CPUCL2_BOOST, "gout_cmu_cpucl2_boost",
1276+
GATE(CLK_GOUT_CMU_CPUCL2_BOOST, "gout_cmu_cpucl2_boost",
12771277
"mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,
12781278
21, 0, 0),
1279-
GATE(CLK_GOUT_MIF_BOOST, "gout_cmu_mif_boost",
1279+
GATE(CLK_GOUT_CMU_MIF_BOOST, "gout_cmu_mif_boost",
12801280
"mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_MIF_BOOST,
12811281
21, 0, 0),
1282-
GATE(CLK_GOUT_MIF_SWITCH, "gout_cmu_mif_switch", "mout_cmu_mif_switch",
1283-
CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),
1284-
GATE(CLK_GOUT_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
1282+
GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch",
1283+
"mout_cmu_mif_switch", CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),
1284+
GATE(CLK_GOUT_CMU_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
12851285
CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0),
1286-
GATE(CLK_GOUT_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
1286+
GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
12871287
CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0),
1288-
GATE(CLK_GOUT_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
1288+
GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
12891289
CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0),
1290-
GATE(CLK_GOUT_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus",
1290+
GATE(CLK_GOUT_CMU_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus",
12911291
CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0),
1292-
GATE(CLK_GOUT_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0",
1292+
GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0",
12931293
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0),
1294-
GATE(CLK_GOUT_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1",
1294+
GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1",
12951295
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0),
1296-
GATE(CLK_GOUT_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2",
1296+
GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2",
12971297
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0),
1298-
GATE(CLK_GOUT_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3",
1298+
GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3",
12991299
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0),
1300-
GATE(CLK_GOUT_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4",
1300+
GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4",
13011301
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0),
1302-
GATE(CLK_GOUT_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5",
1302+
GATE(CLK_GOUT_CMU_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5",
13031303
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0),
1304-
GATE(CLK_GOUT_CIS_CLK6, "gout_cmu_cis_clk6", "mout_cmu_cis_clk6",
1304+
GATE(CLK_GOUT_CMU_CIS_CLK6, "gout_cmu_cis_clk6", "mout_cmu_cis_clk6",
13051305
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 21, 0, 0),
1306-
GATE(CLK_GOUT_CIS_CLK7, "gout_cmu_cis_clk7", "mout_cmu_cis_clk7",
1306+
GATE(CLK_GOUT_CMU_CIS_CLK7, "gout_cmu_cis_clk7", "mout_cmu_cis_clk7",
13071307
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 21, 0, 0),
1308-
GATE(CLK_GOUT_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_cmu_boost",
1308+
GATE(CLK_GOUT_CMU_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_cmu_boost",
13091309
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0),
1310-
GATE(CLK_GOUT_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
1310+
GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
13111311
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
1312-
GATE(CLK_GOUT_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", "mout_cmu_cpucl0_dbg",
1313-
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 21, 0, 0),
1314-
GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch",
1312+
GATE(CLK_GOUT_CMU_CPUCL0_DBG, "gout_cmu_cpucl0_dbg",
1313+
"mout_cmu_cpucl0_dbg", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
1314+
21, 0, 0),
1315+
GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch",
13151316
"mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
13161317
21, 0, 0),
1317-
GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch",
1318+
GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch",
13181319
"mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
13191320
21, 0, 0),
1320-
GATE(CLK_GOUT_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch",
1321+
GATE(CLK_GOUT_CMU_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch",
13211322
"mout_cmu_cpucl2_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
13221323
21, 0, 0),
1323-
GATE(CLK_GOUT_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
1324+
GATE(CLK_GOUT_CMU_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
13241325
CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
1325-
GATE(CLK_GOUT_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus",
1326+
GATE(CLK_GOUT_CMU_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus",
13261327
CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0),
1327-
GATE(CLK_GOUT_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
1328+
GATE(CLK_GOUT_CMU_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
13281329
CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
1329-
GATE(CLK_GOUT_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
1330+
GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
13301331
CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0),
1331-
GATE(CLK_GOUT_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus",
1332+
GATE(CLK_GOUT_CMU_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus",
13321333
CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0),
1333-
GATE(CLK_GOUT_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
1334+
GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
13341335
CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
1335-
GATE(CLK_GOUT_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
1336+
GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
13361337
CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
1337-
GATE(CLK_GOUT_G3AA_G3AA, "gout_cmu_g3aa_g3aa", "mout_cmu_g3aa_g3aa",
1338+
GATE(CLK_GOUT_CMU_G3AA_G3AA, "gout_cmu_g3aa_g3aa", "mout_cmu_g3aa_g3aa",
13381339
CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),
1339-
GATE(CLK_GOUT_G3D_BUSD, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd",
1340+
GATE(CLK_GOUT_CMU_G3D_BUSD, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd",
13401341
CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0),
1341-
GATE(CLK_GOUT_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb",
1342+
GATE(CLK_GOUT_CMU_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb",
13421343
CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0),
1343-
GATE(CLK_GOUT_G3D_SWITCH, "gout_cmu_g3d_switch", "mout_cmu_g3d_switch",
1344-
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
1345-
GATE(CLK_GOUT_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0",
1344+
GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch",
1345+
"mout_cmu_g3d_switch", CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
1346+
21, 0, 0),
1347+
GATE(CLK_GOUT_CMU_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0",
13461348
CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0),
1347-
GATE(CLK_GOUT_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1",
1349+
GATE(CLK_GOUT_CMU_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1",
13481350
CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0),
1349-
GATE(CLK_GOUT_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc",
1351+
GATE(CLK_GOUT_CMU_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc",
13501352
CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0),
13511353
GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
13521354
CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
1353-
GATE(CLK_GOUT_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus",
1355+
GATE(CLK_GOUT_CMU_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus",
13541356
CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
1355-
GATE(CLK_GOUT_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", "mout_cmu_hsi0_dpgtc",
1356-
CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 21, 0, 0),
1357-
GATE(CLK_GOUT_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd",
1357+
GATE(CLK_GOUT_CMU_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc",
1358+
"mout_cmu_hsi0_dpgtc", CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
1359+
21, 0, 0),
1360+
GATE(CLK_GOUT_CMU_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd",
13581361
"mout_cmu_hsi0_usb31drd", CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
13591362
21, 0, 0),
1360-
GATE(CLK_GOUT_HSI0_USBDPDBG, "gout_cmu_hsi0_usbdpdbg",
1363+
GATE(CLK_GOUT_CMU_HSI0_USBDPDBG, "gout_cmu_hsi0_usbdpdbg",
13611364
"mout_cmu_hsi0_usbdpdbg", CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,
13621365
21, 0, 0),
1363-
GATE(CLK_GOUT_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
1366+
GATE(CLK_GOUT_CMU_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
13641367
CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
1365-
GATE(CLK_GOUT_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie",
1368+
GATE(CLK_GOUT_CMU_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie",
13661369
CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0),
1367-
GATE(CLK_GOUT_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
1370+
GATE(CLK_GOUT_CMU_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
13681371
CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
1369-
GATE(CLK_GOUT_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card",
1372+
GATE(CLK_GOUT_CMU_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card",
13701373
"mout_cmu_hsi2_mmc_card", CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,
13711374
21, 0, 0),
1372-
GATE(CLK_GOUT_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie",
1375+
GATE(CLK_GOUT_CMU_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie",
13731376
CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0),
1374-
GATE(CLK_GOUT_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd",
1377+
GATE(CLK_GOUT_CMU_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd",
13751378
"mout_cmu_hsi2_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,
13761379
21, 0, 0),
1377-
GATE(CLK_GOUT_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
1380+
GATE(CLK_GOUT_CMU_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
13781381
CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
1379-
GATE(CLK_GOUT_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
1382+
GATE(CLK_GOUT_CMU_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
13801383
CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
1381-
GATE(CLK_GOUT_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc",
1384+
GATE(CLK_GOUT_CMU_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc",
13821385
CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0),
1383-
GATE(CLK_GOUT_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc",
1386+
GATE(CLK_GOUT_CMU_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc",
13841387
CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0),
1385-
GATE(CLK_GOUT_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc",
1388+
GATE(CLK_GOUT_CMU_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc",
13861389
CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
1387-
GATE(CLK_GOUT_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
1390+
GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
13881391
CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
1389-
GATE(CLK_GOUT_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
1392+
GATE(CLK_GOUT_CMU_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
13901393
CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
1391-
GATE(CLK_GOUT_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
1394+
GATE(CLK_GOUT_CMU_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
13921395
CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
1393-
GATE(CLK_GOUT_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
1396+
GATE(CLK_GOUT_CMU_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
13941397
CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
1395-
GATE(CLK_GOUT_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra",
1398+
GATE(CLK_GOUT_CMU_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra",
13961399
CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
1397-
GATE(CLK_GOUT_PERIC0_BUS, "gout_cmu_peric0_bus", "mout_cmu_peric0_bus",
1398-
CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 21, 0, 0),
1399-
GATE(CLK_GOUT_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip",
1400+
GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus",
1401+
"mout_cmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
1402+
21, 0, 0),
1403+
GATE(CLK_GOUT_CMU_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip",
14001404
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0),
1401-
GATE(CLK_GOUT_PERIC1_BUS, "gout_cmu_peric1_bus", "mout_cmu_peric1_bus",
1402-
CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 21, 0, 0),
1403-
GATE(CLK_GOUT_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",
1405+
GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus",
1406+
"mout_cmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
1407+
21, 0, 0),
1408+
GATE(CLK_GOUT_CMU_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",
14041409
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0),
1405-
GATE(CLK_GOUT_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
1410+
GATE(CLK_GOUT_CMU_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
14061411
CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
1407-
GATE(CLK_GOUT_TOP_CMUREF, "gout_cmu_top_cmuref", "mout_cmu_top_cmuref",
1408-
CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, 21, 0, 0),
1409-
GATE(CLK_GOUT_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",
1412+
GATE(CLK_GOUT_CMU_TOP_CMUREF, "gout_cmu_top_cmuref",
1413+
"mout_cmu_top_cmuref", CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,
1414+
21, 0, 0),
1415+
GATE(CLK_GOUT_CMU_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",
14101416
CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0),
1411-
GATE(CLK_GOUT_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",
1417+
GATE(CLK_GOUT_CMU_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",
14121418
CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0),
1413-
GATE(CLK_GOUT_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", "mout_cmu_tpu_tpuctl",
1414-
CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 21, 0, 0),
1415-
GATE(CLK_GOUT_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",
1419+
GATE(CLK_GOUT_CMU_TPU_TPUCTL, "gout_cmu_tpu_tpuctl",
1420+
"mout_cmu_tpu_tpuctl", CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,
1421+
21, 0, 0),
1422+
GATE(CLK_GOUT_CMU_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",
14161423
CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0),
14171424
};
14181425

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