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Ben Skeggsairlied
Ben Skeggs
authored and
airlied
committed
drm/nouveau/gr/r535: initial support
Adds support for allocating GR classes from RM. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230918202149.4343-41-skeggsb@gmail.com
1 parent b5ce219 commit 361c3cd

17 files changed

Lines changed: 742 additions & 2 deletions

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‎drivers/gpu/drm/nouveau/include/nvif/class.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -194,6 +194,8 @@
194194

195195
#define AMPERE_B /* cl9097.h */ 0x0000c797
196196

197+
#define ADA_A /* cl9097.h */ 0x0000c997
198+
197199
#define NV74_BSP 0x000074b0
198200

199201
#define GT212_MSVLD 0x000085b1
@@ -239,6 +241,7 @@
239241
#define VOLTA_COMPUTE_A 0x0000c3c0
240242
#define TURING_COMPUTE_A 0x0000c5c0
241243
#define AMPERE_COMPUTE_B 0x0000c7c0
244+
#define ADA_COMPUTE_A 0x0000c9c0
242245

243246
#define NV74_CIPHER 0x000074c1
244247
#endif

‎drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,7 @@ struct nvkm_chan {
4242
dma_addr_t addr;
4343
void *ptr;
4444
} mthdbuf;
45+
struct nvkm_vctx *grctx;
4546
} rm;
4647

4748
struct list_head cctxs;

‎drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,4 +55,5 @@ int gp10b_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct n
5555
int gv100_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
5656
int tu102_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
5757
int ga102_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
58+
int ad102_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
5859
#endif

‎drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -176,6 +176,11 @@ struct nvkm_gsp {
176176
u64 rm_bar2_pdb;
177177
} bar;
178178

179+
struct {
180+
u8 gpcs;
181+
u8 tpcs;
182+
} gr;
183+
179184
const struct nvkm_gsp_rm {
180185
void *(*rpc_get)(struct nvkm_gsp *, u32 fn, u32 argc);
181186
void *(*rpc_push)(struct nvkm_gsp *, void *argv, bool wait, u32 repc);

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h‎

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
1+
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl0080_ctrl0080fifo_h__
2+
#define __src_common_sdk_nvidia_inc_ctrl_ctrl0080_ctrl0080fifo_h__
3+
4+
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
5+
6+
/*
7+
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
8+
* SPDX-License-Identifier: MIT
9+
*
10+
* Permission is hereby granted, free of charge, to any person obtaining a
11+
* copy of this software and associated documentation files (the "Software"),
12+
* to deal in the Software without restriction, including without limitation
13+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
14+
* and/or sell copies of the Software, and to permit persons to whom the
15+
* Software is furnished to do so, subject to the following conditions:
16+
*
17+
* The above copyright notice and this permission notice shall be included in
18+
* all copies or substantial portions of the Software.
19+
*
20+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23+
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25+
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26+
* DEALINGS IN THE SOFTWARE.
27+
*/
28+
29+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID 4:0
30+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS (0x00000000)
31+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VLD (0x00000001)
32+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VIDEO (0x00000002)
33+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_MPEG (0x00000003)
34+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_CAPTURE (0x00000004)
35+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_DISPLAY (0x00000005)
36+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_ENCRYPTION (0x00000006)
37+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_POSTPROCESS (0x00000007)
38+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL (0x00000008)
39+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PM (0x00000009)
40+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COMPUTE_PREEMPT (0x0000000a)
41+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PREEMPT (0x0000000b)
42+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SPILL (0x0000000c)
43+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL (0x0000000d)
44+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BETACB (0x0000000e)
45+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV (0x0000000f)
46+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH (0x00000010)
47+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BUNDLE_CB (0x00000011)
48+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL_GLOBAL (0x00000012)
49+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ATTRIBUTE_CB (0x00000013)
50+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV_CB_GLOBAL (0x00000014)
51+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_POOL (0x00000015)
52+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_CTRL_BLK (0x00000016)
53+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_FECS_EVENT (0x00000017)
54+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PRIV_ACCESS_MAP (0x00000018)
55+
#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT (0x00000019)
56+
57+
#endif

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,48 @@
3232

3333
#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3 (0x00000003U)
3434

35+
typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY {
36+
NV_DECLARE_ALIGNED(NvU64 gpuPhysAddr, 8);
37+
NV_DECLARE_ALIGNED(NvU64 gpuVirtAddr, 8);
38+
NV_DECLARE_ALIGNED(NvU64 size, 8);
39+
NvU32 physAttr;
40+
NvU16 bufferId;
41+
NvU8 bInitialize;
42+
NvU8 bNonmapped;
43+
} NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY;
44+
45+
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN 0U
46+
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM 1U
47+
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH 2U
48+
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB 3U
49+
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL 4U
50+
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB 5U
51+
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL 6U
52+
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL 7U
53+
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK 8U
54+
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT 9U
55+
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP 10U
56+
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP 11U
57+
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP 12U
58+
59+
#define NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES 16U
60+
61+
#define NV2080_CTRL_CMD_GPU_PROMOTE_CTX (0x2080012bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID" */
62+
63+
typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS {
64+
NvU32 engineType;
65+
NvHandle hClient;
66+
NvU32 ChID;
67+
NvHandle hChanClient;
68+
NvHandle hObject;
69+
NvHandle hVirtMemory;
70+
NV_DECLARE_ALIGNED(NvU64 virtAddress, 8);
71+
NV_DECLARE_ALIGNED(NvU64 size, 8);
72+
NvU32 entryCount;
73+
// C form: NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES];
74+
NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES], 8);
75+
} NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS;
76+
3577
typedef struct NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS {
3678
NvU32 gpcMask;
3779
} NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS;

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,25 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS {
3838
NvU32 internalDispActiveMask;
3939
} NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS;
4040

41+
#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8
42+
43+
#define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x19
44+
45+
typedef struct NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO {
46+
NvU32 size;
47+
NvU32 alignment;
48+
} NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO;
49+
50+
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO {
51+
NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT];
52+
} NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO;
53+
54+
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS {
55+
NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
56+
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS;
57+
58+
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID" */
59+
4160
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM (0x20800a49) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID" */
4261

4362
typedef struct NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS {

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/nvidia/inc/kernel/gpu/intr/engine_idx.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,4 +34,7 @@
3434

3535
#define MC_ENGINE_IDX_GSP 49
3636

37+
#define MC_ENGINE_IDX_GR 82
38+
#define MC_ENGINE_IDX_GR0 MC_ENGINE_IDX_GR
39+
3740
#endif

‎drivers/gpu/drm/nouveau/nvkm/engine/device/base.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2762,6 +2762,7 @@ nv192_chipset = {
27622762
.disp = { 0x00000001, ad102_disp_new },
27632763
.dma = { 0x00000001, gv100_dma_new },
27642764
.fifo = { 0x00000001, ga102_fifo_new },
2765+
.gr = { 0x00000001, ad102_gr_new },
27652766
.sec2 = { 0x00000001, ga102_sec2_new },
27662767
};
27672768

@@ -2783,6 +2784,7 @@ nv193_chipset = {
27832784
.disp = { 0x00000001, ad102_disp_new },
27842785
.dma = { 0x00000001, gv100_dma_new },
27852786
.fifo = { 0x00000001, ga102_fifo_new },
2787+
.gr = { 0x00000001, ad102_gr_new },
27862788
.sec2 = { 0x00000001, ga102_sec2_new },
27872789
};
27882790

@@ -2804,6 +2806,7 @@ nv194_chipset = {
28042806
.disp = { 0x00000001, ad102_disp_new },
28052807
.dma = { 0x00000001, gv100_dma_new },
28062808
.fifo = { 0x00000001, ga102_fifo_new },
2809+
.gr = { 0x00000001, ad102_gr_new },
28072810
.sec2 = { 0x00000001, ga102_sec2_new },
28082811
};
28092812

@@ -2825,6 +2828,7 @@ nv196_chipset = {
28252828
.disp = { 0x00000001, ad102_disp_new },
28262829
.dma = { 0x00000001, gv100_dma_new },
28272830
.fifo = { 0x00000001, ga102_fifo_new },
2831+
.gr = { 0x00000001, ad102_gr_new },
28282832
.sec2 = { 0x00000001, ga102_sec2_new },
28292833
};
28302834

@@ -2846,6 +2850,7 @@ nv197_chipset = {
28462850
.disp = { 0x00000001, ad102_disp_new },
28472851
.dma = { 0x00000001, gv100_dma_new },
28482852
.fifo = { 0x00000001, ga102_fifo_new },
2853+
.gr = { 0x00000001, ad102_gr_new },
28492854
.sec2 = { 0x00000001, ga102_sec2_new },
28502855
};
28512856

‎drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@
2929
#include <subdev/gsp.h>
3030
#include <subdev/mmu.h>
3131
#include <subdev/vfn.h>
32+
#include <engine/gr.h>
3233

3334
#include <nvhw/drf.h>
3435

@@ -67,6 +68,8 @@ r535_chan_ramfc_clear(struct nvkm_chan *chan)
6768

6869
dma_free_coherent(fifo->engine.subdev.device->dev, fifo->rm.mthdbuf_size,
6970
chan->rm.mthdbuf.ptr, chan->rm.mthdbuf.addr);
71+
72+
nvkm_cgrp_vctx_put(chan->cgrp, &chan->rm.grctx);
7073
}
7174

7275
#define CHID_PER_USERD 8
@@ -76,12 +79,19 @@ r535_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm,
7679
{
7780
struct nvkm_fifo *fifo = chan->cgrp->runl->fifo;
7881
struct nvkm_engn *engn;
82+
struct nvkm_device *device = fifo->engine.subdev.device;
7983
NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS *args;
8084
const int userd_p = chan->id / CHID_PER_USERD;
8185
const int userd_i = chan->id % CHID_PER_USERD;
8286
u32 eT = ~0;
8387
int ret;
8488

89+
if (unlikely(device->gr && !device->gr->engine.subdev.oneinit)) {
90+
ret = nvkm_subdev_oneinit(&device->gr->engine.subdev);
91+
if (ret)
92+
return ret;
93+
}
94+
8595
nvkm_runl_foreach_engn(engn, chan->cgrp->runl) {
8696
eT = engn->id;
8797
break;
@@ -347,6 +357,27 @@ r535_ce = {
347357
.nonstall = r535_engn_nonstall,
348358
};
349359

360+
static int
361+
r535_gr_ctor(struct nvkm_engn *engn, struct nvkm_vctx *vctx, struct nvkm_chan *chan)
362+
{
363+
/* RM requires GR context buffers to remain mapped until after the
364+
* channel has been destroyed (as opposed to after the last gr obj
365+
* has been deleted).
366+
*
367+
* Take an extra ref here, which will be released once the channel
368+
* object has been deleted.
369+
*/
370+
refcount_inc(&vctx->refs);
371+
chan->rm.grctx = vctx;
372+
return 0;
373+
}
374+
375+
static const struct nvkm_engn_func
376+
r535_gr = {
377+
.nonstall = r535_engn_nonstall,
378+
.ctor2 = r535_gr_ctor,
379+
};
380+
350381
static void
351382
r535_runl_allow(struct nvkm_runl *runl, u32 engm)
352383
{
@@ -477,6 +508,9 @@ r535_fifo_runl_ctor(struct nvkm_fifo *fifo)
477508
case NVKM_ENGINE_CE:
478509
engn = nvkm_runl_add(runl, nv2080, &r535_ce, type, inst);
479510
break;
511+
case NVKM_ENGINE_GR:
512+
engn = nvkm_runl_add(runl, nv2080, &r535_gr, type, inst);
513+
break;
480514
case NVKM_ENGINE_SW:
481515
continue;
482516
default:

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