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11 | 11 | #include <linux/of_address.h> |
12 | 12 | #include <linux/of_irq.h> |
13 | 13 | #include <linux/of_platform.h> |
| 14 | +#include <linux/seq_file.h> |
14 | 15 | #include <linux/slab.h> |
15 | 16 | #include <asm/exception.h> |
16 | 17 |
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25 | 26 |
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26 | 27 | struct lpc32xx_irq_chip { |
27 | 28 | void __iomem *base; |
| 29 | + phys_addr_t addr; |
28 | 30 | struct irq_domain *domain; |
29 | | - struct irq_chip chip; |
30 | 31 | }; |
31 | 32 |
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32 | 33 | static struct lpc32xx_irq_chip *lpc32xx_mic_irqc; |
@@ -118,6 +119,24 @@ static int lpc32xx_irq_set_type(struct irq_data *d, unsigned int type) |
118 | 119 | return 0; |
119 | 120 | } |
120 | 121 |
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| 122 | +static void lpc32xx_irq_print_chip(struct irq_data *d, struct seq_file *p) |
| 123 | +{ |
| 124 | + struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d); |
| 125 | + |
| 126 | + if (ic == lpc32xx_mic_irqc) |
| 127 | + seq_printf(p, "%08x.mic", ic->addr); |
| 128 | + else |
| 129 | + seq_printf(p, "%08x.sic", ic->addr); |
| 130 | +} |
| 131 | + |
| 132 | +static const struct irq_chip lpc32xx_chip = { |
| 133 | + .irq_ack = lpc32xx_irq_ack, |
| 134 | + .irq_mask = lpc32xx_irq_mask, |
| 135 | + .irq_unmask = lpc32xx_irq_unmask, |
| 136 | + .irq_set_type = lpc32xx_irq_set_type, |
| 137 | + .irq_print_chip = lpc32xx_irq_print_chip, |
| 138 | +}; |
| 139 | + |
121 | 140 | static void __exception_irq_entry lpc32xx_handle_irq(struct pt_regs *regs) |
122 | 141 | { |
123 | 142 | struct lpc32xx_irq_chip *ic = lpc32xx_mic_irqc; |
@@ -153,7 +172,7 @@ static int lpc32xx_irq_domain_map(struct irq_domain *id, unsigned int virq, |
153 | 172 | struct lpc32xx_irq_chip *ic = id->host_data; |
154 | 173 |
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155 | 174 | irq_set_chip_data(virq, ic); |
156 | | - irq_set_chip_and_handler(virq, &ic->chip, handle_level_irq); |
| 175 | + irq_set_chip_and_handler(virq, &lpc32xx_chip, handle_level_irq); |
157 | 176 | irq_set_status_flags(virq, IRQ_LEVEL); |
158 | 177 | irq_set_noprobe(virq); |
159 | 178 |
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@@ -183,28 +202,19 @@ static int __init lpc32xx_of_ic_init(struct device_node *node, |
183 | 202 | if (!irqc) |
184 | 203 | return -ENOMEM; |
185 | 204 |
|
| 205 | + irqc->addr = addr; |
186 | 206 | irqc->base = of_iomap(node, 0); |
187 | 207 | if (!irqc->base) { |
188 | 208 | pr_err("%pOF: unable to map registers\n", node); |
189 | 209 | kfree(irqc); |
190 | 210 | return -EINVAL; |
191 | 211 | } |
192 | 212 |
|
193 | | - irqc->chip.irq_ack = lpc32xx_irq_ack; |
194 | | - irqc->chip.irq_mask = lpc32xx_irq_mask; |
195 | | - irqc->chip.irq_unmask = lpc32xx_irq_unmask; |
196 | | - irqc->chip.irq_set_type = lpc32xx_irq_set_type; |
197 | | - if (is_mic) |
198 | | - irqc->chip.name = kasprintf(GFP_KERNEL, "%08x.mic", addr); |
199 | | - else |
200 | | - irqc->chip.name = kasprintf(GFP_KERNEL, "%08x.sic", addr); |
201 | | - |
202 | 213 | irqc->domain = irq_domain_add_linear(node, NR_LPC32XX_IC_IRQS, |
203 | 214 | &lpc32xx_irq_domain_ops, irqc); |
204 | 215 | if (!irqc->domain) { |
205 | 216 | pr_err("unable to add irq domain\n"); |
206 | 217 | iounmap(irqc->base); |
207 | | - kfree(irqc->chip.name); |
208 | 218 | kfree(irqc); |
209 | 219 | return -ENODEV; |
210 | 220 | } |
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