@@ -643,27 +643,145 @@ static struct qcom_icc_node xs_sys_tcu_cfg = {
643643 .buswidth = 8 ,
644644};
645645
646- DEFINE_QBCM (bcm_mc0 , "MC0" , true, & ebi );
647- DEFINE_QBCM (bcm_sh0 , "SH0" , true, & qns_llcc );
648- DEFINE_QBCM (bcm_ce0 , "CE0" , false, & qxm_crypto );
649- DEFINE_QBCM (bcm_pn0 , "PN0" , false, & qhm_snoc_cfg );
650- DEFINE_QBCM (bcm_sh3 , "SH3" , false, & xm_apps_rdwr );
651- DEFINE_QBCM (bcm_sh4 , "SH4" , false, & qns_memnoc_snoc , & qns_sys_pcie );
652- DEFINE_QBCM (bcm_sn0 , "SN0" , true, & qns_snoc_memnoc );
653- DEFINE_QBCM (bcm_sn1 , "SN1" , false, & qxs_imem );
654- DEFINE_QBCM (bcm_pn1 , "PN1" , false, & xm_sdc1 );
655- DEFINE_QBCM (bcm_pn2 , "PN2" , false, & qhm_audio , & qhm_spmi_fetcher1 );
656- DEFINE_QBCM (bcm_sn3 , "SN3" , false, & xs_qdss_stm );
657- DEFINE_QBCM (bcm_pn3 , "PN3" , false, & qhm_blsp1 , & qhm_qpic );
658- DEFINE_QBCM (bcm_sn4 , "SN4" , false, & xs_sys_tcu_cfg );
659- DEFINE_QBCM (bcm_pn5 , "PN5" , false, & qxm_crypto );
660- DEFINE_QBCM (bcm_sn6 , "SN6" , false, & xs_pcie );
661- DEFINE_QBCM (bcm_sn7 , "SN7" , false, & qnm_aggre_noc , & xm_emac , & xm_emac , & xm_usb3 ,
662- & qns_aggre_noc );
663- DEFINE_QBCM (bcm_sn8 , "SN8" , false, & qhm_qdss_bam , & xm_qdss_etr );
664- DEFINE_QBCM (bcm_sn9 , "SN9" , false, & qnm_memnoc );
665- DEFINE_QBCM (bcm_sn10 , "SN10" , false, & qnm_memnoc_pcie );
666- DEFINE_QBCM (bcm_sn11 , "SN11" , false, & qnm_ipa , & xm_ipa2pcie_slv );
646+ static struct qcom_icc_bcm bcm_mc0 = {
647+ .name = "MC0" ,
648+ .keepalive = true,
649+ .num_nodes = 1 ,
650+ .nodes = { & ebi },
651+ };
652+
653+ static struct qcom_icc_bcm bcm_sh0 = {
654+ .name = "SH0" ,
655+ .keepalive = true,
656+ .num_nodes = 1 ,
657+ .nodes = { & qns_llcc },
658+ };
659+
660+ static struct qcom_icc_bcm bcm_ce0 = {
661+ .name = "CE0" ,
662+ .keepalive = false,
663+ .num_nodes = 1 ,
664+ .nodes = { & qxm_crypto },
665+ };
666+
667+ static struct qcom_icc_bcm bcm_pn0 = {
668+ .name = "PN0" ,
669+ .keepalive = false,
670+ .num_nodes = 1 ,
671+ .nodes = { & qhm_snoc_cfg },
672+ };
673+
674+ static struct qcom_icc_bcm bcm_sh3 = {
675+ .name = "SH3" ,
676+ .keepalive = false,
677+ .num_nodes = 1 ,
678+ .nodes = { & xm_apps_rdwr },
679+ };
680+
681+ static struct qcom_icc_bcm bcm_sh4 = {
682+ .name = "SH4" ,
683+ .keepalive = false,
684+ .num_nodes = 2 ,
685+ .nodes = { & qns_memnoc_snoc , & qns_sys_pcie },
686+ };
687+
688+ static struct qcom_icc_bcm bcm_sn0 = {
689+ .name = "SN0" ,
690+ .keepalive = true,
691+ .num_nodes = 1 ,
692+ .nodes = { & qns_snoc_memnoc },
693+ };
694+
695+ static struct qcom_icc_bcm bcm_sn1 = {
696+ .name = "SN1" ,
697+ .keepalive = false,
698+ .num_nodes = 1 ,
699+ .nodes = { & qxs_imem },
700+ };
701+
702+ static struct qcom_icc_bcm bcm_pn1 = {
703+ .name = "PN1" ,
704+ .keepalive = false,
705+ .num_nodes = 1 ,
706+ .nodes = { & xm_sdc1 },
707+ };
708+
709+ static struct qcom_icc_bcm bcm_pn2 = {
710+ .name = "PN2" ,
711+ .keepalive = false,
712+ .num_nodes = 2 ,
713+ .nodes = { & qhm_audio , & qhm_spmi_fetcher1 },
714+ };
715+
716+ static struct qcom_icc_bcm bcm_sn3 = {
717+ .name = "SN3" ,
718+ .keepalive = false,
719+ .num_nodes = 1 ,
720+ .nodes = { & xs_qdss_stm },
721+ };
722+
723+ static struct qcom_icc_bcm bcm_pn3 = {
724+ .name = "PN3" ,
725+ .keepalive = false,
726+ .num_nodes = 2 ,
727+ .nodes = { & qhm_blsp1 , & qhm_qpic },
728+ };
729+
730+ static struct qcom_icc_bcm bcm_sn4 = {
731+ .name = "SN4" ,
732+ .keepalive = false,
733+ .num_nodes = 1 ,
734+ .nodes = { & xs_sys_tcu_cfg },
735+ };
736+
737+ static struct qcom_icc_bcm bcm_pn5 = {
738+ .name = "PN5" ,
739+ .keepalive = false,
740+ .num_nodes = 1 ,
741+ .nodes = { & qxm_crypto },
742+ };
743+
744+ static struct qcom_icc_bcm bcm_sn6 = {
745+ .name = "SN6" ,
746+ .keepalive = false,
747+ .num_nodes = 1 ,
748+ .nodes = { & xs_pcie },
749+ };
750+
751+ static struct qcom_icc_bcm bcm_sn7 = {
752+ .name = "SN7" ,
753+ .keepalive = false,
754+ .num_nodes = 5 ,
755+ .nodes = { & qnm_aggre_noc , & xm_emac , & xm_emac , & xm_usb3 , & qns_aggre_noc },
756+ };
757+
758+ static struct qcom_icc_bcm bcm_sn8 = {
759+ .name = "SN8" ,
760+ .keepalive = false,
761+ .num_nodes = 2 ,
762+ .nodes = { & qhm_qdss_bam , & xm_qdss_etr },
763+ };
764+
765+ static struct qcom_icc_bcm bcm_sn9 = {
766+ .name = "SN9" ,
767+ .keepalive = false,
768+ .num_nodes = 1 ,
769+ .nodes = { & qnm_memnoc },
770+ };
771+
772+ static struct qcom_icc_bcm bcm_sn10 = {
773+ .name = "SN10" ,
774+ .keepalive = false,
775+ .num_nodes = 1 ,
776+ .nodes = { & qnm_memnoc_pcie },
777+ };
778+
779+ static struct qcom_icc_bcm bcm_sn11 = {
780+ .name = "SN11" ,
781+ .keepalive = false,
782+ .num_nodes = 2 ,
783+ .nodes = { & qnm_ipa , & xm_ipa2pcie_slv },
784+ };
667785
668786static struct qcom_icc_bcm * const mc_virt_bcms [] = {
669787 & bcm_mc0 ,
0 commit comments