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Merge tag 'qcom-drivers-for-6.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
More Qualcomm driver updates for v6.5 The detection of split/non-split firmware files in the MDT loader is corrected. The Geni driver is updated to not enable unused interrupts, in some configurations. The count unit for MSM8998 in BWMON is corrected. RPM master stats driver is corrected to check for the right return value of devm_ioremap(). Support for socinfo version 18 and 19 are aded, and IPQ5300 is added to the list of platforms. * tag 'qcom-drivers-for-6.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: soc: qcom: geni-se: Do not bother about enable/disable of interrupts in secondary sequencer dt-bindings: sram: qcom,imem: document qdu1000 soc: qcom: icc-bwmon: Fix MSM8998 count unit dt-bindings: soc: qcom,rpmh-rsc: Require power-domains soc: qcom: socinfo: Add Soc ID for IPQ5300 dt-bindings: arm: qcom,ids: add SoC ID for IPQ5300 soc: qcom: Fix a IS_ERR() vs NULL bug in probe soc: qcom: socinfo: Add support for new fields in revision 19 soc: qcom: socinfo: Add support for new fields in revision 18 dt-bindings: firmware: scm: Add compatible for SDX75 soc: qcom: mdt_loader: Fix split image detection Link: https://lore.kernel.org/r/20230615163104.1461905-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents aaeb1b6 + 5d85ea2 commit 37d1fc5

10 files changed

Lines changed: 54 additions & 36 deletions

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‎Documentation/devicetree/bindings/firmware/qcom,scm.yaml‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,7 @@ properties:
5151
- qcom,scm-sdm845
5252
- qcom,scm-sdx55
5353
- qcom,scm-sdx65
54+
- qcom,scm-sdx75
5455
- qcom,scm-sm6115
5556
- qcom,scm-sm6125
5657
- qcom,scm-sm6350

‎Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -124,6 +124,7 @@ required:
124124
- qcom,tcs-offset
125125
- reg
126126
- reg-names
127+
- power-domains
127128

128129
additionalProperties: false
129130

@@ -179,6 +180,7 @@ examples:
179180
<SLEEP_TCS 1>,
180181
<WAKE_TCS 1>,
181182
<CONTROL_TCS 0>;
183+
power-domains = <&CLUSTER_PD>;
182184
};
183185
184186
- |

‎Documentation/devicetree/bindings/sram/qcom,imem.yaml‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@ properties:
2121
- qcom,msm8226-imem
2222
- qcom,msm8974-imem
2323
- qcom,qcs404-imem
24+
- qcom,qdu1000-imem
2425
- qcom,sc7180-imem
2526
- qcom,sc7280-imem
2627
- qcom,sdm630-imem

‎drivers/soc/qcom/icc-bwmon.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -806,7 +806,7 @@ static int bwmon_remove(struct platform_device *pdev)
806806

807807
static const struct icc_bwmon_data msm8998_bwmon_data = {
808808
.sample_ms = 4,
809-
.count_unit_kb = 64,
809+
.count_unit_kb = 1024,
810810
.default_highbw_kbps = 4800 * 1024, /* 4.8 GBps */
811811
.default_medbw_kbps = 512 * 1024, /* 512 MBps */
812812
.default_lowbw_kbps = 0,

‎drivers/soc/qcom/mdt_loader.c‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -275,6 +275,14 @@ static bool qcom_mdt_bins_are_split(const struct firmware *fw, const char *fw_na
275275
phdrs = (struct elf32_phdr *)(ehdr + 1);
276276

277277
for (i = 0; i < ehdr->e_phnum; i++) {
278+
/*
279+
* The size of the MDT file is not padded to include any
280+
* zero-sized segments at the end. Ignore these, as they should
281+
* not affect the decision about image being split or not.
282+
*/
283+
if (!phdrs[i].p_filesz)
284+
continue;
285+
278286
seg_start = phdrs[i].p_offset;
279287
seg_end = phdrs[i].p_offset + phdrs[i].p_filesz;
280288
if (seg_start > fw->size || seg_end > fw->size)

‎drivers/soc/qcom/qcom-geni-se.c‎

Lines changed: 4 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -281,27 +281,14 @@ static void geni_se_select_fifo_mode(struct geni_se *se)
281281

282282
geni_se_irq_clear(se);
283283

284-
/*
285-
* The RX path for the UART is asynchronous and so needs more
286-
* complex logic for enabling / disabling its interrupts.
287-
*
288-
* Specific notes:
289-
* - The done and TX-related interrupts are managed manually.
290-
* - We don't RX from the main sequencer (we use the secondary) so
291-
* we don't need the RX-related interrupts enabled in the main
292-
* sequencer for UART.
293-
*/
284+
/* UART driver manages enabling / disabling interrupts internally */
294285
if (proto != GENI_SE_UART) {
286+
/* Non-UART use only primary sequencer so dont bother about S_IRQ */
295287
val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
296288
val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN;
297289
val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
298290
if (val != val_old)
299291
writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
300-
301-
val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
302-
val |= S_CMD_DONE_EN;
303-
if (val != val_old)
304-
writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
305292
}
306293

307294
val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
@@ -317,17 +304,14 @@ static void geni_se_select_dma_mode(struct geni_se *se)
317304

318305
geni_se_irq_clear(se);
319306

307+
/* UART driver manages enabling / disabling interrupts internally */
320308
if (proto != GENI_SE_UART) {
309+
/* Non-UART use only primary sequencer so dont bother about S_IRQ */
321310
val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
322311
val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
323312
val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
324313
if (val != val_old)
325314
writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
326-
327-
val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
328-
val &= ~S_CMD_DONE_EN;
329-
if (val != val_old)
330-
writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
331315
}
332316

333317
val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
@@ -344,10 +328,6 @@ static void geni_se_select_gpi_mode(struct geni_se *se)
344328

345329
writel(0, se->base + SE_IRQ_EN);
346330

347-
val = readl(se->base + SE_GENI_S_IRQ_EN);
348-
val &= ~S_CMD_DONE_EN;
349-
writel(val, se->base + SE_GENI_S_IRQ_EN);
350-
351331
val = readl(se->base + SE_GENI_M_IRQ_EN);
352332
val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN |
353333
M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);

‎drivers/soc/qcom/rpm_master_stats.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,7 @@ static int master_stats_probe(struct platform_device *pdev)
105105
}
106106

107107
data[i].base = devm_ioremap(dev, res.start, resource_size(&res));
108-
if (IS_ERR(data[i].base)) {
108+
if (!data[i].base) {
109109
debugfs_remove_recursive(root);
110110
return dev_err_probe(dev, -EINVAL,
111111
"Could not map the MSG RAM slice idx %d!\n", i);

‎drivers/soc/qcom/socinfo.c‎

Lines changed: 26 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -133,12 +133,15 @@ struct socinfo_params {
133133
u32 nproduct_id;
134134
u32 num_clusters;
135135
u32 ncluster_array_offset;
136-
u32 num_defective_parts;
137-
u32 ndefective_parts_array_offset;
136+
u32 num_subset_parts;
137+
u32 nsubset_parts_array_offset;
138138
u32 nmodem_supported;
139139
u32 feature_code;
140140
u32 pcode;
141141
u32 oem_variant;
142+
u32 num_func_clusters;
143+
u32 boot_cluster;
144+
u32 boot_core;
142145
};
143146

144147
struct smem_image_version {
@@ -411,6 +414,7 @@ static const struct soc_id soc_id[] = {
411414
{ qcom_board_id(IPQ5322) },
412415
{ qcom_board_id(IPQ5312) },
413416
{ qcom_board_id(IPQ5302) },
417+
{ qcom_board_id(IPQ5300) },
414418
};
415419

416420
static const char *socinfo_machine(struct device *dev, unsigned int id)
@@ -565,6 +569,19 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
565569
&qcom_socinfo->info.fmt);
566570

567571
switch (qcom_socinfo->info.fmt) {
572+
case SOCINFO_VERSION(0, 19):
573+
qcom_socinfo->info.num_func_clusters = __le32_to_cpu(info->num_func_clusters);
574+
qcom_socinfo->info.boot_cluster = __le32_to_cpu(info->boot_cluster);
575+
qcom_socinfo->info.boot_core = __le32_to_cpu(info->boot_core);
576+
577+
debugfs_create_u32("num_func_clusters", 0444, qcom_socinfo->dbg_root,
578+
&qcom_socinfo->info.num_func_clusters);
579+
debugfs_create_u32("boot_cluster", 0444, qcom_socinfo->dbg_root,
580+
&qcom_socinfo->info.boot_cluster);
581+
debugfs_create_u32("boot_core", 0444, qcom_socinfo->dbg_root,
582+
&qcom_socinfo->info.boot_core);
583+
fallthrough;
584+
case SOCINFO_VERSION(0, 18):
568585
case SOCINFO_VERSION(0, 17):
569586
qcom_socinfo->info.oem_variant = __le32_to_cpu(info->oem_variant);
570587
debugfs_create_u32("oem_variant", 0444, qcom_socinfo->dbg_root,
@@ -588,17 +605,18 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
588605
case SOCINFO_VERSION(0, 14):
589606
qcom_socinfo->info.num_clusters = __le32_to_cpu(info->num_clusters);
590607
qcom_socinfo->info.ncluster_array_offset = __le32_to_cpu(info->ncluster_array_offset);
591-
qcom_socinfo->info.num_defective_parts = __le32_to_cpu(info->num_defective_parts);
592-
qcom_socinfo->info.ndefective_parts_array_offset = __le32_to_cpu(info->ndefective_parts_array_offset);
608+
qcom_socinfo->info.num_subset_parts = __le32_to_cpu(info->num_subset_parts);
609+
qcom_socinfo->info.nsubset_parts_array_offset =
610+
__le32_to_cpu(info->nsubset_parts_array_offset);
593611

594612
debugfs_create_u32("num_clusters", 0444, qcom_socinfo->dbg_root,
595613
&qcom_socinfo->info.num_clusters);
596614
debugfs_create_u32("ncluster_array_offset", 0444, qcom_socinfo->dbg_root,
597615
&qcom_socinfo->info.ncluster_array_offset);
598-
debugfs_create_u32("num_defective_parts", 0444, qcom_socinfo->dbg_root,
599-
&qcom_socinfo->info.num_defective_parts);
600-
debugfs_create_u32("ndefective_parts_array_offset", 0444, qcom_socinfo->dbg_root,
601-
&qcom_socinfo->info.ndefective_parts_array_offset);
616+
debugfs_create_u32("num_subset_parts", 0444, qcom_socinfo->dbg_root,
617+
&qcom_socinfo->info.num_subset_parts);
618+
debugfs_create_u32("nsubset_parts_array_offset", 0444, qcom_socinfo->dbg_root,
619+
&qcom_socinfo->info.nsubset_parts_array_offset);
602620
fallthrough;
603621
case SOCINFO_VERSION(0, 13):
604622
qcom_socinfo->info.nproduct_id = __le32_to_cpu(info->nproduct_id);

‎include/dt-bindings/arm/qcom,ids.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -258,6 +258,7 @@
258258
#define QCOM_ID_IPQ5322 593
259259
#define QCOM_ID_IPQ5312 594
260260
#define QCOM_ID_IPQ5302 595
261+
#define QCOM_ID_IPQ5300 624
261262

262263
/*
263264
* The board type and revision information, used by Qualcomm bootloaders and

‎include/linux/soc/qcom/socinfo.h‎

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -54,8 +54,8 @@ struct socinfo {
5454
/* Version 14 */
5555
__le32 num_clusters;
5656
__le32 ncluster_array_offset;
57-
__le32 num_defective_parts;
58-
__le32 ndefective_parts_array_offset;
57+
__le32 num_subset_parts;
58+
__le32 nsubset_parts_array_offset;
5959
/* Version 15 */
6060
__le32 nmodem_supported;
6161
/* Version 16 */
@@ -65,6 +65,13 @@ struct socinfo {
6565
__le32 nnum_partname_mapping;
6666
/* Version 17 */
6767
__le32 oem_variant;
68+
/* Version 18 */
69+
__le32 num_kvps;
70+
__le32 kvps_offset;
71+
/* Version 19 */
72+
__le32 num_func_clusters;
73+
__le32 boot_cluster;
74+
__le32 boot_core;
6875
};
6976

7077
#endif

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