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drm/i915/mtl: Skip MCR ops for ring fault register
On MTL GEN12_RING_FAULT_REG is not replicated so don't do mcr based operation for this register. v2: use MEDIA_VER() instead of GRAPHICS_VER()(Matt). v3: s/"MEDIA_VER(i915) == 13"/"MEDIA_VER(i915) >= 13"(Matt) improve comment. v4: improve the comment further(Andi) Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230928130015.6758-4-nirmoy.das@intel.com
1 parent 37280ef commit 37d6235

3 files changed

Lines changed: 23 additions & 2 deletions

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drivers/gpu/drm/i915/gt/intel_gt.c

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -262,10 +262,21 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
262262
I915_MASTER_ERROR_INTERRUPT);
263263
}
264264

265-
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
265+
/*
266+
* For the media GT, this ring fault register is not replicated,
267+
* so don't do multicast/replicated register read/write operation on it.
268+
*/
269+
if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) {
270+
intel_uncore_rmw(uncore, XELPMP_RING_FAULT_REG,
271+
RING_FAULT_VALID, 0);
272+
intel_uncore_posting_read(uncore,
273+
XELPMP_RING_FAULT_REG);
274+
275+
} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
266276
intel_gt_mcr_multicast_rmw(gt, XEHP_RING_FAULT_REG,
267277
RING_FAULT_VALID, 0);
268278
intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
279+
269280
} else if (GRAPHICS_VER(i915) >= 12) {
270281
intel_uncore_rmw(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID, 0);
271282
intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);

drivers/gpu/drm/i915/gt/intel_gt_regs.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1084,6 +1084,7 @@
10841084

10851085
#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
10861086
#define XEHP_RING_FAULT_REG MCR_REG(0xcec4)
1087+
#define XELPMP_RING_FAULT_REG _MMIO(0xcec4)
10871088
#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
10881089
#define RING_FAULT_GTTSEL_MASK (1 << 11)
10891090
#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)

drivers/gpu/drm/i915/i915_gpu_error.c

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1234,7 +1234,16 @@ static void engine_record_registers(struct intel_engine_coredump *ee)
12341234
if (GRAPHICS_VER(i915) >= 6) {
12351235
ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
12361236

1237-
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
1237+
/*
1238+
* For the media GT, this ring fault register is not replicated,
1239+
* so don't do multicast/replicated register read/write
1240+
* operation on it.
1241+
*/
1242+
if (MEDIA_VER(i915) >= 13 && engine->gt->type == GT_MEDIA)
1243+
ee->fault_reg = intel_uncore_read(engine->uncore,
1244+
XELPMP_RING_FAULT_REG);
1245+
1246+
else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
12381247
ee->fault_reg = intel_gt_mcr_read_any(engine->gt,
12391248
XEHP_RING_FAULT_REG);
12401249
else if (GRAPHICS_VER(i915) >= 12)

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