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airliedairlied
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Merge tag 'amd-drm-fixes-6.5-2023-07-12' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.5-2023-07-12: amdgpu: - SMU i2c locking fix - Fix a possible deadlock in process restoration for ROCm apps - Disable PCIe lane/speed switching on Intel platforms (the platforms don't support it) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230712184009.7740-1-alexander.deucher@amd.com
2 parents 864e029 + e701156 commit 38d88d5

12 files changed

Lines changed: 101 additions & 141 deletions

File tree

‎drivers/gpu/drm/amd/amdgpu/amdgpu.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1296,6 +1296,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
12961296
void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
12971297
int amdgpu_device_pci_reset(struct amdgpu_device *adev);
12981298
bool amdgpu_device_need_post(struct amdgpu_device *adev);
1299+
bool amdgpu_device_pcie_dynamic_switching_supported(void);
12991300
bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
13001301
bool amdgpu_device_aspm_support_quirk(void);
13011302

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2881,6 +2881,9 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
28812881
if (!attachment->is_mapped)
28822882
continue;
28832883

2884+
if (attachment->bo_va->base.bo->tbo.pin_count)
2885+
continue;
2886+
28842887
kfd_mem_dmaunmap_attachment(mem, attachment);
28852888
ret = update_gpuvm_pte(mem, attachment, &sync_obj);
28862889
if (ret) {

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1458,6 +1458,25 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev)
14581458
return true;
14591459
}
14601460

1461+
/*
1462+
* Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic
1463+
* speed switching. Until we have confirmation from Intel that a specific host
1464+
* supports it, it's safer that we keep it disabled for all.
1465+
*
1466+
* https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/
1467+
* https://gitlab.freedesktop.org/drm/amd/-/issues/2663
1468+
*/
1469+
bool amdgpu_device_pcie_dynamic_switching_supported(void)
1470+
{
1471+
#if IS_ENABLED(CONFIG_X86)
1472+
struct cpuinfo_x86 *c = &cpu_data(0);
1473+
1474+
if (c->x86_vendor == X86_VENDOR_INTEL)
1475+
return false;
1476+
#endif
1477+
return true;
1478+
}
1479+
14611480
/**
14621481
* amdgpu_device_should_use_aspm - check if the device should program ASPM
14631482
*

‎drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -295,5 +295,9 @@ int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
295295
uint32_t *size,
296296
uint32_t pptable_id);
297297

298+
int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
299+
uint32_t pcie_gen_cap,
300+
uint32_t pcie_width_cap);
301+
298302
#endif
299303
#endif

‎drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2113,7 +2113,6 @@ static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
21132113
}
21142114
mutex_lock(&adev->pm.mutex);
21152115
r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2116-
mutex_unlock(&adev->pm.mutex);
21172116
if (r)
21182117
goto fail;
21192118

@@ -2130,6 +2129,7 @@ static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
21302129
}
21312130
r = num_msgs;
21322131
fail:
2132+
mutex_unlock(&adev->pm.mutex);
21332133
kfree(req);
21342134
return r;
21352135
}

‎drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3021,7 +3021,6 @@ static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap,
30213021
}
30223022
mutex_lock(&adev->pm.mutex);
30233023
r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3024-
mutex_unlock(&adev->pm.mutex);
30253024
if (r)
30263025
goto fail;
30273026

@@ -3038,6 +3037,7 @@ static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap,
30383037
}
30393038
r = num_msgs;
30403039
fail:
3040+
mutex_unlock(&adev->pm.mutex);
30413041
kfree(req);
30423042
return r;
30433043
}

‎drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c‎

Lines changed: 19 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -2077,89 +2077,36 @@ static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context
20772077
return ret;
20782078
}
20792079

2080-
static void sienna_cichlid_get_override_pcie_settings(struct smu_context *smu,
2081-
uint32_t *gen_speed_override,
2082-
uint32_t *lane_width_override)
2083-
{
2084-
struct amdgpu_device *adev = smu->adev;
2085-
2086-
*gen_speed_override = 0xff;
2087-
*lane_width_override = 0xff;
2088-
2089-
switch (adev->pdev->device) {
2090-
case 0x73A0:
2091-
case 0x73A1:
2092-
case 0x73A2:
2093-
case 0x73A3:
2094-
case 0x73AB:
2095-
case 0x73AE:
2096-
/* Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 */
2097-
*lane_width_override = 6;
2098-
break;
2099-
case 0x73E0:
2100-
case 0x73E1:
2101-
case 0x73E3:
2102-
*lane_width_override = 4;
2103-
break;
2104-
case 0x7420:
2105-
case 0x7421:
2106-
case 0x7422:
2107-
case 0x7423:
2108-
case 0x7424:
2109-
*lane_width_override = 3;
2110-
break;
2111-
default:
2112-
break;
2113-
}
2114-
}
2115-
2116-
#define MAX(a, b) ((a) > (b) ? (a) : (b))
2117-
21182080
static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
21192081
uint32_t pcie_gen_cap,
21202082
uint32_t pcie_width_cap)
21212083
{
21222084
struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
21232085
struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
2124-
uint32_t gen_speed_override, lane_width_override;
2125-
uint8_t *table_member1, *table_member2;
2126-
uint32_t min_gen_speed, max_gen_speed;
2127-
uint32_t min_lane_width, max_lane_width;
2128-
uint32_t smu_pcie_arg;
2086+
u32 smu_pcie_arg;
21292087
int ret, i;
21302088

2131-
GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
2132-
GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
2133-
2134-
sienna_cichlid_get_override_pcie_settings(smu,
2135-
&gen_speed_override,
2136-
&lane_width_override);
2089+
/* PCIE gen speed and lane width override */
2090+
if (!amdgpu_device_pcie_dynamic_switching_supported()) {
2091+
if (pcie_table->pcie_gen[NUM_LINK_LEVELS - 1] < pcie_gen_cap)
2092+
pcie_gen_cap = pcie_table->pcie_gen[NUM_LINK_LEVELS - 1];
21372093

2138-
/* PCIE gen speed override */
2139-
if (gen_speed_override != 0xff) {
2140-
min_gen_speed = MIN(pcie_gen_cap, gen_speed_override);
2141-
max_gen_speed = MIN(pcie_gen_cap, gen_speed_override);
2142-
} else {
2143-
min_gen_speed = MAX(0, table_member1[0]);
2144-
max_gen_speed = MIN(pcie_gen_cap, table_member1[1]);
2145-
min_gen_speed = min_gen_speed > max_gen_speed ?
2146-
max_gen_speed : min_gen_speed;
2147-
}
2148-
pcie_table->pcie_gen[0] = min_gen_speed;
2149-
pcie_table->pcie_gen[1] = max_gen_speed;
2094+
if (pcie_table->pcie_lane[NUM_LINK_LEVELS - 1] < pcie_width_cap)
2095+
pcie_width_cap = pcie_table->pcie_lane[NUM_LINK_LEVELS - 1];
21502096

2151-
/* PCIE lane width override */
2152-
if (lane_width_override != 0xff) {
2153-
min_lane_width = MIN(pcie_width_cap, lane_width_override);
2154-
max_lane_width = MIN(pcie_width_cap, lane_width_override);
2097+
/* Force all levels to use the same settings */
2098+
for (i = 0; i < NUM_LINK_LEVELS; i++) {
2099+
pcie_table->pcie_gen[i] = pcie_gen_cap;
2100+
pcie_table->pcie_lane[i] = pcie_width_cap;
2101+
}
21552102
} else {
2156-
min_lane_width = MAX(1, table_member2[0]);
2157-
max_lane_width = MIN(pcie_width_cap, table_member2[1]);
2158-
min_lane_width = min_lane_width > max_lane_width ?
2159-
max_lane_width : min_lane_width;
2103+
for (i = 0; i < NUM_LINK_LEVELS; i++) {
2104+
if (pcie_table->pcie_gen[i] > pcie_gen_cap)
2105+
pcie_table->pcie_gen[i] = pcie_gen_cap;
2106+
if (pcie_table->pcie_lane[i] > pcie_width_cap)
2107+
pcie_table->pcie_lane[i] = pcie_width_cap;
2108+
}
21602109
}
2161-
pcie_table->pcie_lane[0] = min_lane_width;
2162-
pcie_table->pcie_lane[1] = max_lane_width;
21632110

21642111
for (i = 0; i < NUM_LINK_LEVELS; i++) {
21652112
smu_pcie_arg = (i << 16 |
@@ -3842,7 +3789,6 @@ static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
38423789
}
38433790
mutex_lock(&adev->pm.mutex);
38443791
r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3845-
mutex_unlock(&adev->pm.mutex);
38463792
if (r)
38473793
goto fail;
38483794

@@ -3859,6 +3805,7 @@ static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
38593805
}
38603806
r = num_msgs;
38613807
fail:
3808+
mutex_unlock(&adev->pm.mutex);
38623809
kfree(req);
38633810
return r;
38643811
}

‎drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1525,7 +1525,6 @@ static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
15251525
}
15261526
mutex_lock(&adev->pm.mutex);
15271527
r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1528-
mutex_unlock(&adev->pm.mutex);
15291528
if (r)
15301529
goto fail;
15311530

@@ -1542,6 +1541,7 @@ static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
15421541
}
15431542
r = num_msgs;
15441543
fail:
1544+
mutex_unlock(&adev->pm.mutex);
15451545
kfree(req);
15461546
return r;
15471547
}

‎drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2424,3 +2424,51 @@ int smu_v13_0_mode1_reset(struct smu_context *smu)
24242424

24252425
return ret;
24262426
}
2427+
2428+
int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
2429+
uint32_t pcie_gen_cap,
2430+
uint32_t pcie_width_cap)
2431+
{
2432+
struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2433+
struct smu_13_0_pcie_table *pcie_table =
2434+
&dpm_context->dpm_tables.pcie_table;
2435+
int num_of_levels = pcie_table->num_of_link_levels;
2436+
uint32_t smu_pcie_arg;
2437+
int ret, i;
2438+
2439+
if (!amdgpu_device_pcie_dynamic_switching_supported()) {
2440+
if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
2441+
pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
2442+
2443+
if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
2444+
pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
2445+
2446+
/* Force all levels to use the same settings */
2447+
for (i = 0; i < num_of_levels; i++) {
2448+
pcie_table->pcie_gen[i] = pcie_gen_cap;
2449+
pcie_table->pcie_lane[i] = pcie_width_cap;
2450+
}
2451+
} else {
2452+
for (i = 0; i < num_of_levels; i++) {
2453+
if (pcie_table->pcie_gen[i] > pcie_gen_cap)
2454+
pcie_table->pcie_gen[i] = pcie_gen_cap;
2455+
if (pcie_table->pcie_lane[i] > pcie_width_cap)
2456+
pcie_table->pcie_lane[i] = pcie_width_cap;
2457+
}
2458+
}
2459+
2460+
for (i = 0; i < num_of_levels; i++) {
2461+
smu_pcie_arg = i << 16;
2462+
smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
2463+
smu_pcie_arg |= pcie_table->pcie_lane[i];
2464+
2465+
ret = smu_cmn_send_smc_msg_with_param(smu,
2466+
SMU_MSG_OverridePcieParameters,
2467+
smu_pcie_arg,
2468+
NULL);
2469+
if (ret)
2470+
return ret;
2471+
}
2472+
2473+
return 0;
2474+
}

‎drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c‎

Lines changed: 2 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -1645,37 +1645,6 @@ static int smu_v13_0_0_force_clk_levels(struct smu_context *smu,
16451645
return ret;
16461646
}
16471647

1648-
static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu,
1649-
uint32_t pcie_gen_cap,
1650-
uint32_t pcie_width_cap)
1651-
{
1652-
struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1653-
struct smu_13_0_pcie_table *pcie_table =
1654-
&dpm_context->dpm_tables.pcie_table;
1655-
uint32_t smu_pcie_arg;
1656-
int ret, i;
1657-
1658-
for (i = 0; i < pcie_table->num_of_link_levels; i++) {
1659-
if (pcie_table->pcie_gen[i] > pcie_gen_cap)
1660-
pcie_table->pcie_gen[i] = pcie_gen_cap;
1661-
if (pcie_table->pcie_lane[i] > pcie_width_cap)
1662-
pcie_table->pcie_lane[i] = pcie_width_cap;
1663-
1664-
smu_pcie_arg = i << 16;
1665-
smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
1666-
smu_pcie_arg |= pcie_table->pcie_lane[i];
1667-
1668-
ret = smu_cmn_send_smc_msg_with_param(smu,
1669-
SMU_MSG_OverridePcieParameters,
1670-
smu_pcie_arg,
1671-
NULL);
1672-
if (ret)
1673-
return ret;
1674-
}
1675-
1676-
return 0;
1677-
}
1678-
16791648
static const struct smu_temperature_range smu13_thermal_policy[] = {
16801649
{-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
16811650
{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
@@ -2320,7 +2289,6 @@ static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap,
23202289
}
23212290
mutex_lock(&adev->pm.mutex);
23222291
r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2323-
mutex_unlock(&adev->pm.mutex);
23242292
if (r)
23252293
goto fail;
23262294

@@ -2337,6 +2305,7 @@ static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap,
23372305
}
23382306
r = num_msgs;
23392307
fail:
2308+
mutex_unlock(&adev->pm.mutex);
23402309
kfree(req);
23412310
return r;
23422311
}
@@ -2654,7 +2623,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
26542623
.feature_is_enabled = smu_cmn_feature_is_enabled,
26552624
.print_clk_levels = smu_v13_0_0_print_clk_levels,
26562625
.force_clk_levels = smu_v13_0_0_force_clk_levels,
2657-
.update_pcie_parameters = smu_v13_0_0_update_pcie_parameters,
2626+
.update_pcie_parameters = smu_v13_0_update_pcie_parameters,
26582627
.get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range,
26592628
.register_irq_handler = smu_v13_0_register_irq_handler,
26602629
.enable_thermal_alert = smu_v13_0_enable_thermal_alert,

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