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Merge patch series "pinctrl: intel: Consolidate struct intel_padgroup initialisers"
Andy Shevchenko <andriy.shevchenko@linux.intel.com> says: We have plenty of repetitive *_GPP() macros across the drivers. Consolidate them under a newly introduced INTEL_GPP(). Link: https://patch.msgid.link/20251104145814.1018867-1-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2 parents ce27278 + d99b7a9 commit 396f45a

10 files changed

Lines changed: 199 additions & 262 deletions

‎drivers/pinctrl/intel/pinctrl-alderlake.c‎

Lines changed: 30 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -27,14 +27,6 @@
2727
#define ADL_S_GPI_IS 0x200
2828
#define ADL_S_GPI_IE 0x220
2929

30-
#define ADL_GPP(r, s, e, g) \
31-
{ \
32-
.reg_num = (r), \
33-
.base = (s), \
34-
.size = ((e) - (s) + 1), \
35-
.gpio_base = (g), \
36-
}
37-
3830
#define ADL_N_COMMUNITY(b, s, e, g) \
3931
INTEL_COMMUNITY_GPPS(b, s, e, g, ADL_N)
4032

@@ -316,28 +308,28 @@ static const struct pinctrl_pin_desc adln_pins[] = {
316308
};
317309

318310
static const struct intel_padgroup adln_community0_gpps[] = {
319-
ADL_GPP(0, 0, 25, 0), /* GPP_B */
320-
ADL_GPP(1, 26, 41, 32), /* GPP_T */
321-
ADL_GPP(2, 42, 66, 64), /* GPP_A */
311+
INTEL_GPP(0, 0, 25, 0), /* GPP_B */
312+
INTEL_GPP(1, 26, 41, 32), /* GPP_T */
313+
INTEL_GPP(2, 42, 66, 64), /* GPP_A */
322314
};
323315

324316
static const struct intel_padgroup adln_community1_gpps[] = {
325-
ADL_GPP(0, 67, 74, 96), /* GPP_S */
326-
ADL_GPP(1, 75, 94, 128), /* GPP_I */
327-
ADL_GPP(2, 95, 118, 160), /* GPP_H */
328-
ADL_GPP(3, 119, 139, 192), /* GPP_D */
329-
ADL_GPP(4, 140, 168, 224), /* vGPIO */
317+
INTEL_GPP(0, 67, 74, 96), /* GPP_S */
318+
INTEL_GPP(1, 75, 94, 128), /* GPP_I */
319+
INTEL_GPP(2, 95, 118, 160), /* GPP_H */
320+
INTEL_GPP(3, 119, 139, 192), /* GPP_D */
321+
INTEL_GPP(4, 140, 168, 224), /* vGPIO */
330322
};
331323

332324
static const struct intel_padgroup adln_community4_gpps[] = {
333-
ADL_GPP(0, 169, 192, 256), /* GPP_C */
334-
ADL_GPP(1, 193, 217, 288), /* GPP_F */
335-
ADL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
336-
ADL_GPP(3, 224, 248, 320), /* GPP_E */
325+
INTEL_GPP(0, 169, 192, 256), /* GPP_C */
326+
INTEL_GPP(1, 193, 217, 288), /* GPP_F */
327+
INTEL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
328+
INTEL_GPP(3, 224, 248, 320), /* GPP_E */
337329
};
338330

339331
static const struct intel_padgroup adln_community5_gpps[] = {
340-
ADL_GPP(0, 249, 256, 352), /* GPP_R */
332+
INTEL_GPP(0, 249, 256, 352), /* GPP_R */
341333
};
342334

343335
static const struct intel_community adln_communities[] = {
@@ -680,35 +672,35 @@ static const struct pinctrl_pin_desc adls_pins[] = {
680672
};
681673

682674
static const struct intel_padgroup adls_community0_gpps[] = {
683-
ADL_GPP(0, 0, 24, 0), /* GPP_I */
684-
ADL_GPP(1, 25, 47, 32), /* GPP_R */
685-
ADL_GPP(2, 48, 59, 64), /* GPP_J */
686-
ADL_GPP(3, 60, 86, 96), /* vGPIO */
687-
ADL_GPP(4, 87, 94, 128), /* vGPIO_0 */
675+
INTEL_GPP(0, 0, 24, 0), /* GPP_I */
676+
INTEL_GPP(1, 25, 47, 32), /* GPP_R */
677+
INTEL_GPP(2, 48, 59, 64), /* GPP_J */
678+
INTEL_GPP(3, 60, 86, 96), /* vGPIO */
679+
INTEL_GPP(4, 87, 94, 128), /* vGPIO_0 */
688680
};
689681

690682
static const struct intel_padgroup adls_community1_gpps[] = {
691-
ADL_GPP(0, 95, 118, 160), /* GPP_B */
692-
ADL_GPP(1, 119, 126, 192), /* GPP_G */
693-
ADL_GPP(2, 127, 150, 224), /* GPP_H */
683+
INTEL_GPP(0, 95, 118, 160), /* GPP_B */
684+
INTEL_GPP(1, 119, 126, 192), /* GPP_G */
685+
INTEL_GPP(2, 127, 150, 224), /* GPP_H */
694686
};
695687

696688
static const struct intel_padgroup adls_community3_gpps[] = {
697-
ADL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP), /* SPI0 */
698-
ADL_GPP(1, 160, 175, 256), /* GPP_A */
699-
ADL_GPP(2, 176, 199, 288), /* GPP_C */
689+
INTEL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP), /* SPI0 */
690+
INTEL_GPP(1, 160, 175, 256), /* GPP_A */
691+
INTEL_GPP(2, 176, 199, 288), /* GPP_C */
700692
};
701693

702694
static const struct intel_padgroup adls_community4_gpps[] = {
703-
ADL_GPP(0, 200, 207, 320), /* GPP_S */
704-
ADL_GPP(1, 208, 230, 352), /* GPP_E */
705-
ADL_GPP(2, 231, 245, 384), /* GPP_K */
706-
ADL_GPP(3, 246, 269, 416), /* GPP_F */
695+
INTEL_GPP(0, 200, 207, 320), /* GPP_S */
696+
INTEL_GPP(1, 208, 230, 352), /* GPP_E */
697+
INTEL_GPP(2, 231, 245, 384), /* GPP_K */
698+
INTEL_GPP(3, 246, 269, 416), /* GPP_F */
707699
};
708700

709701
static const struct intel_padgroup adls_community5_gpps[] = {
710-
ADL_GPP(0, 270, 294, 448), /* GPP_D */
711-
ADL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP), /* JTAG */
702+
INTEL_GPP(0, 270, 294, 448), /* GPP_D */
703+
INTEL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP), /* JTAG */
712704
};
713705

714706
static const struct intel_community adls_communities[] = {

‎drivers/pinctrl/intel/pinctrl-cannonlake.c‎

Lines changed: 30 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -28,14 +28,6 @@
2828
#define CNL_H_GPI_IS 0x100
2929
#define CNL_H_GPI_IE 0x120
3030

31-
#define CNL_GPP(r, s, e, g) \
32-
{ \
33-
.reg_num = (r), \
34-
.base = (s), \
35-
.size = ((e) - (s) + 1), \
36-
.gpio_base = (g), \
37-
}
38-
3931
#define CNL_LP_COMMUNITY(b, s, e, g) \
4032
INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_LP)
4133

@@ -362,32 +354,32 @@ static const struct pinctrl_pin_desc cnlh_pins[] = {
362354
};
363355

364356
static const struct intel_padgroup cnlh_community0_gpps[] = {
365-
CNL_GPP(0, 0, 24, 0), /* GPP_A */
366-
CNL_GPP(1, 25, 50, 32), /* GPP_B */
357+
INTEL_GPP(0, 0, 24, 0), /* GPP_A */
358+
INTEL_GPP(1, 25, 50, 32), /* GPP_B */
367359
};
368360

369361
static const struct intel_padgroup cnlh_community1_gpps[] = {
370-
CNL_GPP(0, 51, 74, 64), /* GPP_C */
371-
CNL_GPP(1, 75, 98, 96), /* GPP_D */
372-
CNL_GPP(2, 99, 106, 128), /* GPP_G */
373-
CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */
374-
CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */
375-
CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */
362+
INTEL_GPP(0, 51, 74, 64), /* GPP_C */
363+
INTEL_GPP(1, 75, 98, 96), /* GPP_D */
364+
INTEL_GPP(2, 99, 106, 128), /* GPP_G */
365+
INTEL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */
366+
INTEL_GPP(4, 115, 146, 160), /* vGPIO_0 */
367+
INTEL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */
376368
};
377369

378370
static const struct intel_padgroup cnlh_community3_gpps[] = {
379-
CNL_GPP(0, 155, 178, 192), /* GPP_K */
380-
CNL_GPP(1, 179, 202, 224), /* GPP_H */
381-
CNL_GPP(2, 203, 215, 256), /* GPP_E */
382-
CNL_GPP(3, 216, 239, 288), /* GPP_F */
383-
CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */
371+
INTEL_GPP(0, 155, 178, 192), /* GPP_K */
372+
INTEL_GPP(1, 179, 202, 224), /* GPP_H */
373+
INTEL_GPP(2, 203, 215, 256), /* GPP_E */
374+
INTEL_GPP(3, 216, 239, 288), /* GPP_F */
375+
INTEL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */
384376
};
385377

386378
static const struct intel_padgroup cnlh_community4_gpps[] = {
387-
CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */
388-
CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */
389-
CNL_GPP(2, 269, 286, 320), /* GPP_I */
390-
CNL_GPP(3, 287, 298, 352), /* GPP_J */
379+
INTEL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */
380+
INTEL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */
381+
INTEL_GPP(2, 269, 286, 320), /* GPP_I */
382+
INTEL_GPP(3, 287, 298, 352), /* GPP_J */
391383
};
392384

393385
static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
@@ -780,25 +772,25 @@ static const struct intel_function cnllp_functions[] = {
780772
};
781773

782774
static const struct intel_padgroup cnllp_community0_gpps[] = {
783-
CNL_GPP(0, 0, 24, 0), /* GPP_A */
784-
CNL_GPP(1, 25, 50, 32), /* GPP_B */
785-
CNL_GPP(2, 51, 58, 64), /* GPP_G */
786-
CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */
775+
INTEL_GPP(0, 0, 24, 0), /* GPP_A */
776+
INTEL_GPP(1, 25, 50, 32), /* GPP_B */
777+
INTEL_GPP(2, 51, 58, 64), /* GPP_G */
778+
INTEL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */
787779
};
788780

789781
static const struct intel_padgroup cnllp_community1_gpps[] = {
790-
CNL_GPP(0, 68, 92, 96), /* GPP_D */
791-
CNL_GPP(1, 93, 116, 128), /* GPP_F */
792-
CNL_GPP(2, 117, 140, 160), /* GPP_H */
793-
CNL_GPP(3, 141, 172, 192), /* vGPIO */
794-
CNL_GPP(4, 173, 180, 224), /* vGPIO */
782+
INTEL_GPP(0, 68, 92, 96), /* GPP_D */
783+
INTEL_GPP(1, 93, 116, 128), /* GPP_F */
784+
INTEL_GPP(2, 117, 140, 160), /* GPP_H */
785+
INTEL_GPP(3, 141, 172, 192), /* vGPIO */
786+
INTEL_GPP(4, 173, 180, 224), /* vGPIO */
795787
};
796788

797789
static const struct intel_padgroup cnllp_community4_gpps[] = {
798-
CNL_GPP(0, 181, 204, 256), /* GPP_C */
799-
CNL_GPP(1, 205, 228, 288), /* GPP_E */
800-
CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */
801-
CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
790+
INTEL_GPP(0, 181, 204, 256), /* GPP_C */
791+
INTEL_GPP(1, 205, 228, 288), /* GPP_E */
792+
INTEL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */
793+
INTEL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
802794
};
803795

804796
static const struct intel_community cnllp_communities[] = {

‎drivers/pinctrl/intel/pinctrl-icelake.c‎

Lines changed: 26 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -28,14 +28,6 @@
2828
#define ICL_N_GPI_IS 0x100
2929
#define ICL_N_GPI_IE 0x120
3030

31-
#define ICL_GPP(r, s, e, g) \
32-
{ \
33-
.reg_num = (r), \
34-
.base = (s), \
35-
.size = ((e) - (s) + 1), \
36-
.gpio_base = (g), \
37-
}
38-
3931
#define ICL_LP_COMMUNITY(b, s, e, g) \
4032
INTEL_COMMUNITY_GPPS(b, s, e, g, ICL_LP)
4133

@@ -302,29 +294,29 @@ static const struct pinctrl_pin_desc icllp_pins[] = {
302294
};
303295

304296
static const struct intel_padgroup icllp_community0_gpps[] = {
305-
ICL_GPP(0, 0, 7, 0), /* GPP_G */
306-
ICL_GPP(1, 8, 33, 32), /* GPP_B */
307-
ICL_GPP(2, 34, 58, 64), /* GPP_A */
297+
INTEL_GPP(0, 0, 7, 0), /* GPP_G */
298+
INTEL_GPP(1, 8, 33, 32), /* GPP_B */
299+
INTEL_GPP(2, 34, 58, 64), /* GPP_A */
308300
};
309301

310302
static const struct intel_padgroup icllp_community1_gpps[] = {
311-
ICL_GPP(0, 59, 82, 96), /* GPP_H */
312-
ICL_GPP(1, 83, 103, 128), /* GPP_D */
313-
ICL_GPP(2, 104, 123, 160), /* GPP_F */
314-
ICL_GPP(3, 124, 152, 192), /* vGPIO */
303+
INTEL_GPP(0, 59, 82, 96), /* GPP_H */
304+
INTEL_GPP(1, 83, 103, 128), /* GPP_D */
305+
INTEL_GPP(2, 104, 123, 160), /* GPP_F */
306+
INTEL_GPP(3, 124, 152, 192), /* vGPIO */
315307
};
316308

317309
static const struct intel_padgroup icllp_community4_gpps[] = {
318-
ICL_GPP(0, 153, 176, 224), /* GPP_C */
319-
ICL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
320-
ICL_GPP(2, 183, 206, 256), /* GPP_E */
321-
ICL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */
310+
INTEL_GPP(0, 153, 176, 224), /* GPP_C */
311+
INTEL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
312+
INTEL_GPP(2, 183, 206, 256), /* GPP_E */
313+
INTEL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */
322314
};
323315

324316
static const struct intel_padgroup icllp_community5_gpps[] = {
325-
ICL_GPP(0, 216, 223, 288), /* GPP_R */
326-
ICL_GPP(1, 224, 231, 320), /* GPP_S */
327-
ICL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */
317+
INTEL_GPP(0, 216, 223, 288), /* GPP_R */
318+
INTEL_GPP(1, 224, 231, 320), /* GPP_S */
319+
INTEL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */
328320
};
329321

330322
static const struct intel_community icllp_communities[] = {
@@ -632,27 +624,27 @@ static const struct pinctrl_pin_desc icln_pins[] = {
632624
};
633625

634626
static const struct intel_padgroup icln_community0_gpps[] = {
635-
ICL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP), /* SPI */
636-
ICL_GPP(1, 9, 34, 32), /* GPP_B */
637-
ICL_GPP(2, 35, 55, 64), /* GPP_A */
638-
ICL_GPP(3, 56, 63, 96), /* GPP_S */
639-
ICL_GPP(4, 64, 71, 128), /* GPP_R */
627+
INTEL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP), /* SPI */
628+
INTEL_GPP(1, 9, 34, 32), /* GPP_B */
629+
INTEL_GPP(2, 35, 55, 64), /* GPP_A */
630+
INTEL_GPP(3, 56, 63, 96), /* GPP_S */
631+
INTEL_GPP(4, 64, 71, 128), /* GPP_R */
640632
};
641633

642634
static const struct intel_padgroup icln_community1_gpps[] = {
643-
ICL_GPP(0, 72, 95, 160), /* GPP_H */
644-
ICL_GPP(1, 96, 121, 192), /* GPP_D */
645-
ICL_GPP(2, 122, 150, 224), /* vGPIO */
646-
ICL_GPP(3, 151, 174, 256), /* GPP_C */
635+
INTEL_GPP(0, 72, 95, 160), /* GPP_H */
636+
INTEL_GPP(1, 96, 121, 192), /* GPP_D */
637+
INTEL_GPP(2, 122, 150, 224), /* vGPIO */
638+
INTEL_GPP(3, 151, 174, 256), /* GPP_C */
647639
};
648640

649641
static const struct intel_padgroup icln_community4_gpps[] = {
650-
ICL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
651-
ICL_GPP(1, 181, 204, 288), /* GPP_E */
642+
INTEL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
643+
INTEL_GPP(1, 181, 204, 288), /* GPP_E */
652644
};
653645

654646
static const struct intel_padgroup icln_community5_gpps[] = {
655-
ICL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO), /* GPP_G */
647+
INTEL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO), /* GPP_G */
656648
};
657649

658650
static const struct intel_community icln_communities[] = {

‎drivers/pinctrl/intel/pinctrl-intel.h‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,15 @@ enum {
7676
INTEL_GPIO_BASE_MATCH = 0,
7777
};
7878

79+
/* Initialise struct intel_padgroup */
80+
#define INTEL_GPP(r, s, e, g) \
81+
{ \
82+
.reg_num = (r), \
83+
.base = (s), \
84+
.size = ((e) - (s) + 1), \
85+
.gpio_base = (g), \
86+
}
87+
7988
/**
8089
* struct intel_community - Intel pin community description
8190
* @barno: MMIO BAR number where registers for this community reside

‎drivers/pinctrl/intel/pinctrl-jasperlake.c‎

Lines changed: 13 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -21,14 +21,6 @@
2121
#define JSL_GPI_IS 0x100
2222
#define JSL_GPI_IE 0x120
2323

24-
#define JSL_GPP(r, s, e, g) \
25-
{ \
26-
.reg_num = (r), \
27-
.base = (s), \
28-
.size = ((e) - (s) + 1), \
29-
.gpio_base = (g), \
30-
}
31-
3224
#define JSL_COMMUNITY(b, s, e, g) \
3325
INTEL_COMMUNITY_GPPS(b, s, e, g, JSL)
3426

@@ -283,28 +275,28 @@ static const struct pinctrl_pin_desc jsl_pins[] = {
283275
};
284276

285277
static const struct intel_padgroup jsl_community0_gpps[] = {
286-
JSL_GPP(0, 0, 19, 320), /* GPP_F */
287-
JSL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP), /* SPI */
288-
JSL_GPP(2, 29, 54, 32), /* GPP_B */
289-
JSL_GPP(3, 55, 75, 64), /* GPP_A */
290-
JSL_GPP(4, 76, 83, 96), /* GPP_S */
291-
JSL_GPP(5, 84, 91, 128), /* GPP_R */
278+
INTEL_GPP(0, 0, 19, 320), /* GPP_F */
279+
INTEL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP), /* SPI */
280+
INTEL_GPP(2, 29, 54, 32), /* GPP_B */
281+
INTEL_GPP(3, 55, 75, 64), /* GPP_A */
282+
INTEL_GPP(4, 76, 83, 96), /* GPP_S */
283+
INTEL_GPP(5, 84, 91, 128), /* GPP_R */
292284
};
293285

294286
static const struct intel_padgroup jsl_community1_gpps[] = {
295-
JSL_GPP(0, 92, 115, 160), /* GPP_H */
296-
JSL_GPP(1, 116, 141, 192), /* GPP_D */
297-
JSL_GPP(2, 142, 170, 224), /* vGPIO */
298-
JSL_GPP(3, 171, 194, 256), /* GPP_C */
287+
INTEL_GPP(0, 92, 115, 160), /* GPP_H */
288+
INTEL_GPP(1, 116, 141, 192), /* GPP_D */
289+
INTEL_GPP(2, 142, 170, 224), /* vGPIO */
290+
INTEL_GPP(3, 171, 194, 256), /* GPP_C */
299291
};
300292

301293
static const struct intel_padgroup jsl_community4_gpps[] = {
302-
JSL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
303-
JSL_GPP(1, 201, 224, 288), /* GPP_E */
294+
INTEL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
295+
INTEL_GPP(1, 201, 224, 288), /* GPP_E */
304296
};
305297

306298
static const struct intel_padgroup jsl_community5_gpps[] = {
307-
JSL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO), /* GPP_G */
299+
INTEL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO), /* GPP_G */
308300
};
309301

310302
static const struct intel_community jsl_communities[] = {

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