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Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git
2 parents 825a5a6 + fa55e63 commit 3b30814

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Lines changed: 1411 additions & 58 deletions

‎Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc‎

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Original file line numberDiff line numberDiff line change
@@ -91,3 +91,19 @@ Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
9191
Description: (RW) Size of the trace buffer for TMC-ETR when used in SYSFS
9292
mode. Writable only for TMC-ETR configurations. The value
9393
should be aligned to the kernel pagesize.
94+
95+
What: /sys/bus/coresight/devices/<memory_map>.tmc/buf_modes_available
96+
Date: August 2023
97+
KernelVersion: 6.7
98+
Contact: Anshuman Khandual <anshuman.khandual@arm.com>
99+
Description: (Read) Shows all supported Coresight TMC-ETR buffer modes available
100+
for the users to configure explicitly. This file is avaialble only
101+
for TMC ETR devices.
102+
103+
What: /sys/bus/coresight/devices/<memory_map>.tmc/buf_mode_preferred
104+
Date: August 2023
105+
KernelVersion: 6.7
106+
Contact: Anshuman Khandual <anshuman.khandual@arm.com>
107+
Description: (RW) Current Coresight TMC-ETR buffer mode selected. But user could
108+
only provide a mode which is supported for a given ETR device. This
109+
file is available only for TMC ETR devices.

‎Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm‎

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Original file line numberDiff line numberDiff line change
@@ -11,3 +11,162 @@ Description:
1111
Accepts only one of the 2 values - 1 or 2.
1212
1 : Generate 64 bits data
1313
2 : Generate 32 bits data
14+
15+
What: /sys/bus/coresight/devices/<tpdm-name>/reset_dataset
16+
Date: March 2023
17+
KernelVersion 6.7
18+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
19+
Description:
20+
(Write) Reset the dataset of the tpdm.
21+
22+
Accepts only one value - 1.
23+
1 : Reset the dataset of the tpdm
24+
25+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type
26+
Date: March 2023
27+
KernelVersion 6.7
28+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
29+
Description:
30+
(RW) Set/Get the trigger type of the DSB for tpdm.
31+
32+
Accepts only one of the 2 values - 0 or 1.
33+
0 : Set the DSB trigger type to false
34+
1 : Set the DSB trigger type to true
35+
36+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts
37+
Date: March 2023
38+
KernelVersion 6.7
39+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
40+
Description:
41+
(RW) Set/Get the trigger timestamp of the DSB for tpdm.
42+
43+
Accepts only one of the 2 values - 0 or 1.
44+
0 : Set the DSB trigger type to false
45+
1 : Set the DSB trigger type to true
46+
47+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_mode
48+
Date: March 2023
49+
KernelVersion 6.7
50+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
51+
Description:
52+
(RW) Set/Get the programming mode of the DSB for tpdm.
53+
54+
Accepts the value needs to be greater than 0. What data
55+
bits do is listed below.
56+
Bit[0:1] : Test mode control bit for choosing the inputs.
57+
Bit[3] : Set to 0 for low performance mode. Set to 1 for high
58+
performance mode.
59+
Bit[4:8] : Select byte lane for high performance mode.
60+
61+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx
62+
Date: March 2023
63+
KernelVersion 6.7
64+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
65+
Description:
66+
(RW) Set/Get the index number of the edge detection for the DSB
67+
subunit TPDM. Since there are at most 256 edge detections, this
68+
value ranges from 0 to 255.
69+
70+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val
71+
Date: March 2023
72+
KernelVersion 6.7
73+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
74+
Description:
75+
Write a data to control the edge detection corresponding to
76+
the index number. Before writing data to this sysfs file,
77+
"ctrl_idx" should be written first to configure the index
78+
number of the edge detection which needs to be controlled.
79+
80+
Accepts only one of the following values.
81+
0 - Rising edge detection
82+
1 - Falling edge detection
83+
2 - Rising and falling edge detection (toggle detection)
84+
85+
86+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask
87+
Date: March 2023
88+
KernelVersion 6.7
89+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
90+
Description:
91+
Write a data to mask the edge detection corresponding to the index
92+
number. Before writing data to this sysfs file, "ctrl_idx" should
93+
be written first to configure the index number of the edge detection
94+
which needs to be masked.
95+
96+
Accepts only one of the 2 values - 0 or 1.
97+
98+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15]
99+
Date: March 2023
100+
KernelVersion 6.7
101+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
102+
Description:
103+
Read a set of the edge control value of the DSB in TPDM.
104+
105+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7]
106+
Date: March 2023
107+
KernelVersion 6.7
108+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
109+
Description:
110+
Read a set of the edge control mask of the DSB in TPDM.
111+
112+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpr[0:7]
113+
Date: March 2023
114+
KernelVersion 6.7
115+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
116+
Description:
117+
(RW) Set/Get the value of the trigger pattern for the DSB
118+
subunit TPDM.
119+
120+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpmr[0:7]
121+
Date: March 2023
122+
KernelVersion 6.7
123+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
124+
Description:
125+
(RW) Set/Get the mask of the trigger pattern for the DSB
126+
subunit TPDM.
127+
128+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:7]
129+
Date: March 2023
130+
KernelVersion 6.7
131+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
132+
Description:
133+
(RW) Set/Get the value of the pattern for the DSB subunit TPDM.
134+
135+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:7]
136+
Date: March 2023
137+
KernelVersion 6.7
138+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
139+
Description:
140+
(RW) Set/Get the mask of the pattern for the DSB subunit TPDM.
141+
142+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/enable_ts
143+
Date: March 2023
144+
KernelVersion 6.7
145+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
146+
Description:
147+
(Write) Set the pattern timestamp of DSB tpdm. Read
148+
the pattern timestamp of DSB tpdm.
149+
150+
Accepts only one of the 2 values - 0 or 1.
151+
0 : Disable DSB pattern timestamp.
152+
1 : Enable DSB pattern timestamp.
153+
154+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/set_type
155+
Date: March 2023
156+
KernelVersion 6.7
157+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
158+
Description:
159+
(Write) Set the pattern type of DSB tpdm. Read
160+
the pattern type of DSB tpdm.
161+
162+
Accepts only one of the 2 values - 0 or 1.
163+
0 : Set the DSB pattern type to value.
164+
1 : Set the DSB pattern type to toggle.
165+
166+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31]
167+
Date: March 2023
168+
KernelVersion 6.7
169+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
170+
Description:
171+
(RW) Set/Get the MSR(mux select register) for the DSB subunit
172+
TPDM.

‎Documentation/arch/arm64/silicon-errata.rst‎

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Original file line numberDiff line numberDiff line change
@@ -117,6 +117,10 @@ stable kernels.
117117
+----------------+-----------------+-----------------+-----------------------------+
118118
| ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
119119
+----------------+-----------------+-----------------+-----------------------------+
120+
| ARM | Cortex-A76 | #1490853 | N/A |
121+
+----------------+-----------------+-----------------+-----------------------------+
122+
| ARM | Cortex-A77 | #1491015 | N/A |
123+
+----------------+-----------------+-----------------+-----------------------------+
120124
| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
121125
+----------------+-----------------+-----------------+-----------------------------+
122126
| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
@@ -127,6 +131,8 @@ stable kernels.
127131
+----------------+-----------------+-----------------+-----------------------------+
128132
| ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_2645198 |
129133
+----------------+-----------------+-----------------+-----------------------------+
134+
| ARM | Cortex-X1 | #1502854 | N/A |
135+
+----------------+-----------------+-----------------+-----------------------------+
130136
| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
131137
+----------------+-----------------+-----------------+-----------------------------+
132138
| ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 |
@@ -135,6 +141,8 @@ stable kernels.
135141
+----------------+-----------------+-----------------+-----------------------------+
136142
| ARM | Neoverse-N1 | #1349291 | N/A |
137143
+----------------+-----------------+-----------------+-----------------------------+
144+
| ARM | Neoverse-N1 | #1490853 | N/A |
145+
+----------------+-----------------+-----------------+-----------------------------+
138146
| ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
139147
+----------------+-----------------+-----------------+-----------------------------+
140148
| ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 |
@@ -143,6 +151,8 @@ stable kernels.
143151
+----------------+-----------------+-----------------+-----------------------------+
144152
| ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 |
145153
+----------------+-----------------+-----------------+-----------------------------+
154+
| ARM | Neoverse-V1 | #1619801 | N/A |
155+
+----------------+-----------------+-----------------+-----------------------------+
146156
| ARM | MMU-500 | #841119,826419 | N/A |
147157
+----------------+-----------------+-----------------+-----------------------------+
148158
| ARM | MMU-600 | #1076982,1209401| N/A |

‎Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -44,6 +44,23 @@ properties:
4444
minItems: 1
4545
maxItems: 2
4646

47+
qcom,dsb-element-size:
48+
description:
49+
Specifies the DSB(Discrete Single Bit) element size supported by
50+
the monitor. The associated aggregator will read this size before it
51+
is enabled. DSB element size currently only supports 32-bit and 64-bit.
52+
$ref: /schemas/types.yaml#/definitions/uint8
53+
enum: [32, 64]
54+
55+
qcom,dsb-msrs-num:
56+
description:
57+
Specifies the number of DSB(Discrete Single Bit) MSR(mux select register)
58+
registers supported by the monitor. If this property is not configured
59+
or set to 0, it means this DSB TPDM doesn't support MSR.
60+
$ref: /schemas/types.yaml#/definitions/uint32
61+
minimum: 0
62+
maximum: 32
63+
4764
clocks:
4865
maxItems: 1
4966

@@ -77,6 +94,9 @@ examples:
7794
compatible = "qcom,coresight-tpdm", "arm,primecell";
7895
reg = <0x0684c000 0x1000>;
7996
97+
qcom,dsb-element-size = /bits/ 8 <32>;
98+
qcom,dsb-msrs-num = <16>;
99+
80100
clocks = <&aoss_qmp>;
81101
clock-names = "apb_pclk";
82102

‎Documentation/trace/coresight/coresight.rst‎

Lines changed: 5 additions & 1 deletion
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@@ -130,7 +130,7 @@ Misc:
130130
Device Tree Bindings
131131
--------------------
132132

133-
See Documentation/devicetree/bindings/arm/arm,coresight-\*.yaml for details.
133+
See ``Documentation/devicetree/bindings/arm/arm,coresight-*.yaml`` for details.
134134

135135
As of this writing drivers for ITM, STMs and CTIs are not provided but are
136136
expected to be added as the solution matures.
@@ -624,6 +624,10 @@ They are also listed in the folder /sys/bus/event_source/devices/cs_etm/format/
624624
* - timestamp
625625
- Session local version of the system wide setting: :ref:`ETMv4_MODE_TIMESTAMP
626626
<coresight-timestamp>`
627+
* - cc_threshold
628+
- Cycle count threshold value. If nothing is provided here or the provided value is 0, then the
629+
default value i.e 0x100 will be used. If provided value is less than minimum cycles threshold
630+
value, as indicated via TRCIDR3.CCITMIN, then the minimum value will be used instead.
627631

628632
How to use the STM module
629633
-------------------------

‎MAINTAINERS‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2059,7 +2059,6 @@ ARM/CORESIGHT FRAMEWORK AND DRIVERS
20592059
M: Suzuki K Poulose <suzuki.poulose@arm.com>
20602060
R: Mike Leach <mike.leach@linaro.org>
20612061
R: James Clark <james.clark@arm.com>
2062-
R: Leo Yan <leo.yan@linaro.org>
20632062
L: coresight@lists.linaro.org (moderated for non-subscribers)
20642063
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
20652064
S: Maintained

‎drivers/hwtracing/coresight/coresight-core.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1093,6 +1093,7 @@ static int coresight_validate_source(struct coresight_device *csdev,
10931093

10941094
if (subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_PROC &&
10951095
subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE &&
1096+
subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM &&
10961097
subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS) {
10971098
dev_err(&csdev->dev, "wrong device subtype in %s\n", function);
10981099
return -EINVAL;
@@ -1162,6 +1163,7 @@ int coresight_enable(struct coresight_device *csdev)
11621163
per_cpu(tracer_path, cpu) = path;
11631164
break;
11641165
case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
1166+
case CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM:
11651167
case CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS:
11661168
/*
11671169
* Use the hash of source's device name as ID
@@ -1212,6 +1214,7 @@ void coresight_disable(struct coresight_device *csdev)
12121214
per_cpu(tracer_path, cpu) = NULL;
12131215
break;
12141216
case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
1217+
case CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM:
12151218
case CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS:
12161219
hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev)));
12171220
/* Find the path by the hash. */

‎drivers/hwtracing/coresight/coresight-etm-perf.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,7 @@ PMU_FORMAT_ATTR(preset, "config:0-3");
6868
PMU_FORMAT_ATTR(sinkid, "config2:0-31");
6969
/* config ID - set if a system configuration is selected */
7070
PMU_FORMAT_ATTR(configid, "config2:32-63");
71+
PMU_FORMAT_ATTR(cc_threshold, "config3:0-11");
7172

7273

7374
/*
@@ -101,6 +102,7 @@ static struct attribute *etm_config_formats_attr[] = {
101102
&format_attr_preset.attr,
102103
&format_attr_configid.attr,
103104
&format_attr_branch_broadcast.attr,
105+
&format_attr_cc_threshold.attr,
104106
NULL,
105107
};
106108

@@ -493,7 +495,7 @@ static void etm_event_start(struct perf_event *event, int flags)
493495
goto fail_end_stop;
494496

495497
/* Finally enable the tracer */
496-
if (coresight_enable_source(csdev, CS_MODE_PERF, event))
498+
if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF))
497499
goto fail_disable_path;
498500

499501
/*
@@ -587,7 +589,7 @@ static void etm_event_stop(struct perf_event *event, int mode)
587589
return;
588590

589591
/* stop tracer */
590-
coresight_disable_source(csdev, event);
592+
source_ops(csdev)->disable(csdev, event);
591593

592594
/* tell the core */
593595
event->hw.state = PERF_HES_STOPPED;

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