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vadimp-nvidiajwrdegoede
vadimp-nvidia
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platform: mellanox: mlx-platform: add support for additional CPLD
Extend to support 5-th CPLD version, PN and minimal version registers. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Link: https://lore.kernel.org/r/20230822113451.13785-7-vadimp@nvidia.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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‎drivers/platform/x86/mlx-platform.c‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -95,6 +95,9 @@
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#define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88
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#define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89
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#define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a
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#define MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET 0x8e
99+
#define MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET 0x8f
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#define MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET 0x90
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#define MLXPLAT_CPLD_LPC_REG_EROT_OFFSET 0x91
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#define MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET 0x92
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#define MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET 0x93
@@ -129,6 +132,7 @@
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#define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0xb9
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#define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0xc2
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#define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0xc3
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#define MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET 0xc4
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#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7
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#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8
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#define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9
@@ -3431,6 +3435,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
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.bit = GENMASK(7, 0),
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.mode = 0444,
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},
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{
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.label = "cpld5_version",
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.reg = MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET,
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.bit = GENMASK(7, 0),
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.mode = 0444,
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},
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{
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.label = "cpld1_pn",
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.reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
@@ -3459,6 +3469,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
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.mode = 0444,
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.regnum = 2,
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},
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{
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.label = "cpld5_pn",
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.reg = MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET,
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.bit = GENMASK(15, 0),
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.mode = 0444,
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.regnum = 2,
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},
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{
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.label = "cpld1_version_min",
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.reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
@@ -3483,6 +3500,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
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.bit = GENMASK(7, 0),
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.mode = 0444,
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},
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{
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.label = "cpld5_version_min",
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.reg = MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET,
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.bit = GENMASK(7, 0),
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.mode = 0444,
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},
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{
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.label = "asic_reset",
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.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
@@ -5031,6 +5054,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
@@ -5039,6 +5063,8 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
@@ -5150,6 +5176,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET:
@@ -5191,6 +5218,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
@@ -5199,6 +5227,8 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
@@ -5302,6 +5332,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET:

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