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Merge tag 'qcom-drivers-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers
Qualcomm driver updates for v5.19 This converts a wide range of Qualcomm-related DeviceTree bindings to YAML, in order to improve our ability to validate the DeviceTree source. The RPMh power-domain driver gains support for the modem platform SDX65, the compute platform SC8280XP and the automotive platform SA8540p. While LLCC gains support for SC8180X and SC8280XP and gains a MODULE_DEVICE_TABLE() to make it functional as a module. It adds a driver for configuring the SSC bus, providing Linux access to the hardware blocks in the sensor subsystem. The socinfo driver gets confusion related to MSM8974 Pro sorted out and adds new ids for SM8540 and SC7280. The SCM driver gains support for MSM8974. Add missing of_node_put() in smp2p and smsm drivers. Stop using iterator after list_for_each_entry() and define static definitions as such, in the PDR driver. * tag 'qcom-drivers-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (33 commits) soc: qcom: pdr: use static for servreg_* variables soc: qcom: llcc: Add sc8180x and sc8280xp configurations dt-bindings: arm: msm: Add sc8180x and sc8280xp LLCC compatibles soc: qcom: rpmhpd: add sc8280xp & sa8540p rpmh power-domains soc: qcom: rpmhpd: Don't warn about sparse rpmhpd arrays dt-bindings: power: rpmpd: Add sc8280xp RPMh power-domains spi: dt-bindings: qcom,spi-geni-qcom: convert to dtschema soc: qcom: socinfo: Sort out 8974PRO names dt-bindings: soc: qcom,smp2p: convert to dtschema dt-bindings: qcom: geni-se: Update UART schema reference dt-bindings: qcom: geni-se: Update I2C schema reference dt-bindings: soc: qcom,rpmh-rsc: convert to dtschema bus: add driver for initializing the SSC bus on (some) qcom SoCs dt-bindings: bus: add device tree bindings for qcom,ssc-block-bus dt-bindings: qcom: qcom,geni-se: refer to dtschema for SPI dt-bindings: soc: qcom,smd: convert to dtschema firmware: qcom_scm: Add compatible for MSM8976 SoC dt-bindings: firmware: qcom-scm: Document msm8976 bindings soc: qcom: smem: validate fields of shared structures soc: qcom: smem: map only partitions used by local HOST ... Link: https://lore.kernel.org/r/20220509181839.316655-1-bjorn.andersson@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents 6e6962f + 28e3dc8 commit 3f656f2

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‎Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml‎

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enum:
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- qcom,sc7180-llcc
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- qcom,sc7280-llcc
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- qcom,sc8180x-llcc
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- qcom,sc8280xp-llcc
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- qcom,sdm845-llcc
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- qcom,sm6350-llcc
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- qcom,sm8150-llcc

‎Documentation/devicetree/bindings/arm/qcom.yaml‎

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msm8994
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msm8996
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sa8155p
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sa8540p
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sc7180
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sc7280
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sc8180x
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sc8280xp
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sdm630
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sdm632
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sdm660
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- google,senor
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- const: qcom,sc7280
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- items:
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- enum:
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- lenovo,flex-5g
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- microsoft,surface-prox
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- qcom,sc8180x-primus
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- const: qcom,sc8180x
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- items:
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- enum:
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- qcom,sc8280xp-qrd
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- const: qcom,sc8280xp
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- items:
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- enum:
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- fairphone,fp3
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- qcom,sa8155p-adp
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- const: qcom,sa8155p
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- items:
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- enum:
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- qcom,sa8295p-adp
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- const: qcom,sa8540p
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- items:
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- enum:
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- fairphone,fp4

‎Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs
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maintainers:
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- Michael Srba <Michael.Srba@seznam.cz>
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description: |
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This binding describes the dependencies (clocks, resets, power domains) which
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need to be turned on in a sequence before communication over the AHB bus
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becomes possible.
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Additionally, the reg property is used to pass to the driver the location of
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two sadly undocumented registers which need to be poked as part of the sequence.
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The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart
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controllers, a hexagon core, and a clock controller which provides clocks for
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the above.
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properties:
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compatible:
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items:
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- const: qcom,msm8998-ssc-block-bus
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- const: qcom,ssc-block-bus
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reg:
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description: |
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Shall contain the addresses of the SSCAON_CONFIG0 and SSCAON_CONFIG1
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registers
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minItems: 2
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maxItems: 2
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reg-names:
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items:
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- const: mpm_sscaon_config0
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- const: mpm_sscaon_config1
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'#address-cells':
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enum: [ 1, 2 ]
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'#size-cells':
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enum: [ 1, 2 ]
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ranges: true
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clocks:
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minItems: 6
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maxItems: 6
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clock-names:
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items:
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- const: xo
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- const: aggre2
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- const: gcc_im_sleep
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- const: aggre2_north
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- const: ssc_xo
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- const: ssc_ahbs
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power-domains:
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description: Power domain phandles for the ssc_cx and ssc_mx power domains
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minItems: 2
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maxItems: 2
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power-domain-names:
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items:
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- const: ssc_cx
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- const: ssc_mx
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resets:
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description: |
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Reset phandles for the ssc_reset and ssc_bcr resets (note: ssc_bcr is the
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branch control register associated with the ssc_xo and ssc_ahbs clocks)
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minItems: 2
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maxItems: 2
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reset-names:
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items:
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- const: ssc_reset
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- const: ssc_bcr
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qcom,halt-regs:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: describes how to locate the ssc AXI halt register
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items:
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- items:
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- description: Phandle reference to a syscon representing TCSR
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- description: offset for the ssc AXI halt register
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required:
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- compatible
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- reg
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- reg-names
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- '#address-cells'
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- '#size-cells'
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- ranges
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- clocks
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- clock-names
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- power-domains
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- power-domain-names
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- resets
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- reset-names
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- qcom,halt-regs
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additionalProperties:
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type: object
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-msm8998.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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// devices under this node are physically located in the SSC block, connected to an ssc-internal bus;
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ssc_ahb_slave: bus@10ac008 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus";
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reg = <0x10ac008 0x4>, <0x10ac010 0x4>;
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reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1";
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clocks = <&xo>,
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<&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
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<&gcc GCC_IM_SLEEP>,
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<&gcc AGGRE2_SNOC_NORTH_AXI>,
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<&gcc SSC_XO>,
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<&gcc SSC_CNOC_AHBS_CLK>;
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clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs";
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resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>;
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reset-names = "ssc_reset", "ssc_bcr";
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power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>;
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power-domain-names = "ssc_cx", "ssc_mx";
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qcom,halt-regs = <&tcsr_mutex_regs 0x26000>;
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};
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};

‎Documentation/devicetree/bindings/firmware/qcom,scm.txt‎

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* "qcom,scm-msm8953"
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* "qcom,scm-msm8960"
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* "qcom,scm-msm8974"
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* "qcom,scm-msm8976"
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* "qcom,scm-msm8994"
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* "qcom,scm-msm8996"
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* "qcom,scm-msm8998"
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* core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660" and
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"qcom,scm-msm8960"
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* core, iface and bus clocks required for "qcom,scm-apq8084",
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"qcom,scm-msm8916", "qcom,scm-msm8953" and "qcom,scm-msm8974"
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"qcom,scm-msm8916", "qcom,scm-msm8953", "qcom,scm-msm8974" and "qcom,scm-msm8976"
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- clock-names: Must contain "core" for the core clock, "iface" for the interface
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clock and "bus" for the bus clock per the requirements of the compatible.
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- qcom,dload-mode: phandle to the TCSR hardware block and offset of the

‎Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml‎

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examples:
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# Example 1: apps bcm_voter on SDM845 SoC should be defined inside &apps_rsc node
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# as defined in Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
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# as defined in Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
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- |
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apps_bcm_voter: bcm_voter {
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apps_bcm_voter: bcm-voter {
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compatible = "qcom,bcm-voter";
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};
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# Example 2: disp bcm_voter on SDM845 should be defined inside &disp_rsc node
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# as defined in Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
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# as defined in Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
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- |
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#include <dt-bindings/interconnect/qcom,icc.h>
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disp_bcm_voter: bcm_voter {
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disp_bcm_voter: bcm-voter {
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compatible = "qcom,bcm-voter";
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qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
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};

‎Documentation/devicetree/bindings/power/qcom,rpmpd.yaml‎

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- qcom,msm8998-rpmpd
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- qcom,qcm2290-rpmpd
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- qcom,qcs404-rpmpd
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- qcom,sa8540p-rpmhpd
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- qcom,sdm660-rpmpd
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- qcom,sc7180-rpmhpd
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- qcom,sc7280-rpmhpd
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- qcom,sc8180x-rpmhpd
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- qcom,sc8280xp-rpmhpd
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- qcom,sdm845-rpmhpd
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- qcom,sdx55-rpmhpd
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- qcom,sdx65-rpmhpd
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- qcom,sm6115-rpmpd
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- qcom,sm6125-rpmpd
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- qcom,sm6350-rpmhpd

‎Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml‎

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resides as a subnode of the SMD. As such, the SMD-RPM regulator requires
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that the SMD and RPM nodes be present.
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Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,smd.txt for
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Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml for
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information pertaining to the SMD node.
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Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
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l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22
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maintainers:
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- Kathiravan T <kathirav@codeaurora.org>
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- Andy Gross <agross@kernel.org>
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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properties:
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compatible:

‎Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt‎

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The Hexagon node may also have an subnode named either "smd-edge" or
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"glink-edge" that describes the communication edge, channels and devices
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related to the Hexagon. See ../soc/qcom/qcom,smd.txt and
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related to the Hexagon. See ../soc/qcom/qcom,smd.yaml and
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../soc/qcom/qcom,glink.txt for details on how to describe these.
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= EXAMPLE

‎Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt‎

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The wcnss node can also have an subnode named "smd-edge" that describes the SMD
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edge, channels and devices related to the WCNSS.
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See ../soc/qcom/qcom,smd.txt for details on how to describe the SMD edge.
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See ../soc/qcom/qcom,smd.yaml for details on how to describe the SMD edge.
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= EXAMPLE
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The following example describes the resources needed to boot control the WCNSS,

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