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simingwaherbertx
simingwa
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crypto: qat - expand CSR operations for QAT GEN4 devices
Extend the CSR operations for QAT GEN4 devices to allow saving and restoring the rings state. The new operations will be used as a building block for implementing the state save and restore of Virtual Functions necessary for VM live migration. This adds the following operations: - read ring status register - read ring underflow/overflow status register - read ring nearly empty status register - read ring nearly full status register - read ring full status register - read ring complete status register - read ring exception status register - read/write ring exception interrupt mask register - read ring configuration register - read ring base register - read/write ring interrupt enable register - read ring interrupt flag register - read/write ring interrupt source select register - read ring coalesced interrupt enable register - read ring coalesced interrupt control register - read ring flag and coalesced interrupt enable register - read ring service arbiter enable register - get ring coalesced interrupt control enable mask Signed-off-by: Siming Wan <siming.wan@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Xin Zeng <xin.zeng@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
1 parent 84058ff commit 3fa1057

3 files changed

Lines changed: 249 additions & 1 deletion

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‎drivers/crypto/intel/qat/qat_common/adf_accel_devices.h‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -150,22 +150,49 @@ struct adf_hw_csr_ops {
150150
u32 ring);
151151
void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
152152
u32 ring, u32 value);
153+
u32 (*read_csr_stat)(void __iomem *csr_base_addr, u32 bank);
154+
u32 (*read_csr_uo_stat)(void __iomem *csr_base_addr, u32 bank);
153155
u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);
156+
u32 (*read_csr_ne_stat)(void __iomem *csr_base_addr, u32 bank);
157+
u32 (*read_csr_nf_stat)(void __iomem *csr_base_addr, u32 bank);
158+
u32 (*read_csr_f_stat)(void __iomem *csr_base_addr, u32 bank);
159+
u32 (*read_csr_c_stat)(void __iomem *csr_base_addr, u32 bank);
160+
u32 (*read_csr_exp_stat)(void __iomem *csr_base_addr, u32 bank);
161+
u32 (*read_csr_exp_int_en)(void __iomem *csr_base_addr, u32 bank);
162+
void (*write_csr_exp_int_en)(void __iomem *csr_base_addr, u32 bank,
163+
u32 value);
164+
u32 (*read_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
165+
u32 ring);
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void (*write_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
155167
u32 ring, u32 value);
168+
dma_addr_t (*read_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
169+
u32 ring);
156170
void (*write_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
157171
u32 ring, dma_addr_t addr);
172+
u32 (*read_csr_int_en)(void __iomem *csr_base_addr, u32 bank);
173+
void (*write_csr_int_en)(void __iomem *csr_base_addr, u32 bank,
174+
u32 value);
175+
u32 (*read_csr_int_flag)(void __iomem *csr_base_addr, u32 bank);
158176
void (*write_csr_int_flag)(void __iomem *csr_base_addr, u32 bank,
159177
u32 value);
178+
u32 (*read_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
160179
void (*write_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
180+
void (*write_csr_int_srcsel_w_val)(void __iomem *csr_base_addr,
181+
u32 bank, u32 value);
182+
u32 (*read_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank);
161183
void (*write_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank,
162184
u32 value);
185+
u32 (*read_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank);
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void (*write_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank,
164187
u32 value);
188+
u32 (*read_csr_int_flag_and_col)(void __iomem *csr_base_addr,
189+
u32 bank);
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void (*write_csr_int_flag_and_col)(void __iomem *csr_base_addr,
166191
u32 bank, u32 value);
192+
u32 (*read_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank);
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void (*write_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank,
168194
u32 value);
195+
u32 (*get_int_col_ctl_enable_mask)(void);
169196
};
170197

171198
struct adf_cfg_device_data;

‎drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c‎

Lines changed: 130 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,72 +30,202 @@ static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,
3030
WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
3131
}
3232

33+
static u32 read_csr_stat(void __iomem *csr_base_addr, u32 bank)
34+
{
35+
return READ_CSR_STAT(csr_base_addr, bank);
36+
}
37+
38+
static u32 read_csr_uo_stat(void __iomem *csr_base_addr, u32 bank)
39+
{
40+
return READ_CSR_UO_STAT(csr_base_addr, bank);
41+
}
42+
3343
static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)
3444
{
3545
return READ_CSR_E_STAT(csr_base_addr, bank);
3646
}
3747

48+
static u32 read_csr_ne_stat(void __iomem *csr_base_addr, u32 bank)
49+
{
50+
return READ_CSR_NE_STAT(csr_base_addr, bank);
51+
}
52+
53+
static u32 read_csr_nf_stat(void __iomem *csr_base_addr, u32 bank)
54+
{
55+
return READ_CSR_NF_STAT(csr_base_addr, bank);
56+
}
57+
58+
static u32 read_csr_f_stat(void __iomem *csr_base_addr, u32 bank)
59+
{
60+
return READ_CSR_F_STAT(csr_base_addr, bank);
61+
}
62+
63+
static u32 read_csr_c_stat(void __iomem *csr_base_addr, u32 bank)
64+
{
65+
return READ_CSR_C_STAT(csr_base_addr, bank);
66+
}
67+
68+
static u32 read_csr_exp_stat(void __iomem *csr_base_addr, u32 bank)
69+
{
70+
return READ_CSR_EXP_STAT(csr_base_addr, bank);
71+
}
72+
73+
static u32 read_csr_exp_int_en(void __iomem *csr_base_addr, u32 bank)
74+
{
75+
return READ_CSR_EXP_INT_EN(csr_base_addr, bank);
76+
}
77+
78+
static void write_csr_exp_int_en(void __iomem *csr_base_addr, u32 bank,
79+
u32 value)
80+
{
81+
WRITE_CSR_EXP_INT_EN(csr_base_addr, bank, value);
82+
}
83+
84+
static u32 read_csr_ring_config(void __iomem *csr_base_addr, u32 bank,
85+
u32 ring)
86+
{
87+
return READ_CSR_RING_CONFIG(csr_base_addr, bank, ring);
88+
}
89+
3890
static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank, u32 ring,
3991
u32 value)
4092
{
4193
WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
4294
}
4395

96+
static dma_addr_t read_csr_ring_base(void __iomem *csr_base_addr, u32 bank,
97+
u32 ring)
98+
{
99+
return READ_CSR_RING_BASE(csr_base_addr, bank, ring);
100+
}
101+
44102
static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring,
45103
dma_addr_t addr)
46104
{
47105
WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);
48106
}
49107

108+
static u32 read_csr_int_en(void __iomem *csr_base_addr, u32 bank)
109+
{
110+
return READ_CSR_INT_EN(csr_base_addr, bank);
111+
}
112+
113+
static void write_csr_int_en(void __iomem *csr_base_addr, u32 bank, u32 value)
114+
{
115+
WRITE_CSR_INT_EN(csr_base_addr, bank, value);
116+
}
117+
118+
static u32 read_csr_int_flag(void __iomem *csr_base_addr, u32 bank)
119+
{
120+
return READ_CSR_INT_FLAG(csr_base_addr, bank);
121+
}
122+
50123
static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank,
51124
u32 value)
52125
{
53126
WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);
54127
}
55128

129+
static u32 read_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
130+
{
131+
return READ_CSR_INT_SRCSEL(csr_base_addr, bank);
132+
}
133+
56134
static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
57135
{
58136
WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);
59137
}
60138

139+
static void write_csr_int_srcsel_w_val(void __iomem *csr_base_addr, u32 bank,
140+
u32 value)
141+
{
142+
WRITE_CSR_INT_SRCSEL_W_VAL(csr_base_addr, bank, value);
143+
}
144+
145+
static u32 read_csr_int_col_en(void __iomem *csr_base_addr, u32 bank)
146+
{
147+
return READ_CSR_INT_COL_EN(csr_base_addr, bank);
148+
}
149+
61150
static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank, u32 value)
62151
{
63152
WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);
64153
}
65154

155+
static u32 read_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank)
156+
{
157+
return READ_CSR_INT_COL_CTL(csr_base_addr, bank);
158+
}
159+
66160
static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank,
67161
u32 value)
68162
{
69163
WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);
70164
}
71165

166+
static u32 read_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank)
167+
{
168+
return READ_CSR_INT_FLAG_AND_COL(csr_base_addr, bank);
169+
}
170+
72171
static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,
73172
u32 value)
74173
{
75174
WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
76175
}
77176

177+
static u32 read_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank)
178+
{
179+
return READ_CSR_RING_SRV_ARB_EN(csr_base_addr, bank);
180+
}
181+
78182
static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,
79183
u32 value)
80184
{
81185
WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
82186
}
83187

188+
static u32 get_int_col_ctl_enable_mask(void)
189+
{
190+
return ADF_RING_CSR_INT_COL_CTL_ENABLE;
191+
}
192+
84193
void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
85194
{
86195
csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
87196
csr_ops->read_csr_ring_head = read_csr_ring_head;
88197
csr_ops->write_csr_ring_head = write_csr_ring_head;
89198
csr_ops->read_csr_ring_tail = read_csr_ring_tail;
90199
csr_ops->write_csr_ring_tail = write_csr_ring_tail;
200+
csr_ops->read_csr_stat = read_csr_stat;
201+
csr_ops->read_csr_uo_stat = read_csr_uo_stat;
91202
csr_ops->read_csr_e_stat = read_csr_e_stat;
203+
csr_ops->read_csr_ne_stat = read_csr_ne_stat;
204+
csr_ops->read_csr_nf_stat = read_csr_nf_stat;
205+
csr_ops->read_csr_f_stat = read_csr_f_stat;
206+
csr_ops->read_csr_c_stat = read_csr_c_stat;
207+
csr_ops->read_csr_exp_stat = read_csr_exp_stat;
208+
csr_ops->read_csr_exp_int_en = read_csr_exp_int_en;
209+
csr_ops->write_csr_exp_int_en = write_csr_exp_int_en;
210+
csr_ops->read_csr_ring_config = read_csr_ring_config;
92211
csr_ops->write_csr_ring_config = write_csr_ring_config;
212+
csr_ops->read_csr_ring_base = read_csr_ring_base;
93213
csr_ops->write_csr_ring_base = write_csr_ring_base;
214+
csr_ops->read_csr_int_en = read_csr_int_en;
215+
csr_ops->write_csr_int_en = write_csr_int_en;
216+
csr_ops->read_csr_int_flag = read_csr_int_flag;
94217
csr_ops->write_csr_int_flag = write_csr_int_flag;
218+
csr_ops->read_csr_int_srcsel = read_csr_int_srcsel;
95219
csr_ops->write_csr_int_srcsel = write_csr_int_srcsel;
220+
csr_ops->write_csr_int_srcsel_w_val = write_csr_int_srcsel_w_val;
221+
csr_ops->read_csr_int_col_en = read_csr_int_col_en;
96222
csr_ops->write_csr_int_col_en = write_csr_int_col_en;
223+
csr_ops->read_csr_int_col_ctl = read_csr_int_col_ctl;
97224
csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
225+
csr_ops->read_csr_int_flag_and_col = read_csr_int_flag_and_col;
98226
csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
227+
csr_ops->read_csr_ring_srv_arb_en = read_csr_ring_srv_arb_en;
99228
csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
229+
csr_ops->get_int_col_ctl_enable_mask = get_int_col_ctl_enable_mask;
100230
}
101231
EXPORT_SYMBOL_GPL(adf_gen4_init_hw_csr_ops);

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