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dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document lanes mapping when not using in USB-C complex
The QMP USB3/DP Combo PHY hosts an USB3 phy and a DP PHY on top of a combo glue to route either lanes to the 4 shared physical lanes. The routing of the lanes can be: - 2 DP + 2 USB3 - 4 DP - 2 USB3 The layout of the lanes was designed to be mapped and swapped related to the USB-C Power Delivery negociation, so it supports a finite set of mappings inherited by the USB-C Altmode layouts. Nevertheless those QMP Comby PHY can be used to drive a DisplayPort connector, DP->HDMI bridge, USB3 A Connector, etc... without an USB-C connector and no PD events. Document the data-lanes on numbered port@0 out endpoints, allowing us to document the lanes mapping to DisplayPort and/or USB3 connectors/peripherals. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-topic-x1e80100-hdmi-v7-1-2bee0e66cc1b@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml

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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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$ref: /schemas/graph.yaml#/$defs/port-base
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description: Output endpoint of the PHY
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unevaluatedProperties: false
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properties:
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endpoint:
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$ref: /schemas/graph.yaml#/$defs/endpoint-base
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unevaluatedProperties: false
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endpoint@0:
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$ref: /schemas/graph.yaml#/$defs/endpoint-base
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description: Display Port Output lanes of the PHY when used with static mapping,
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The entry index is the DP lanes index, and the number is the PHY
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signal in the order RX0, TX0, TX1, RX1.
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unevaluatedProperties: false
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properties:
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# Static lane mappings are mutually exclusive with typec-mux/orientation-mux
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data-lanes:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 2
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maxItems: 4
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oneOf:
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- items: # DisplayPort 1 lane, normal orientation
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- const: 3
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- items: # DisplayPort 1 lane, flipped orientation
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- const: 0
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- items: # DisplayPort 2 lanes, normal orientation
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- const: 3
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- const: 2
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- items: # DisplayPort 2 lanes, flipped orientation
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- const: 0
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- const: 1
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- items: # DisplayPort 4 lanes, normal orientation
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- const: 3
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- const: 2
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- const: 1
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- const: 0
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- items: # DisplayPort 4 lanes, flipped orientation
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- const: 0
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- const: 1
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- const: 2
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- const: 3
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required:
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- data-lanes
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endpoint@1:
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$ref: /schemas/graph.yaml#/$defs/endpoint-base
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description: USB Output lanes of the PHY when used with static mapping.
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The entry index is the USB3 lane in the order TX then RX, and the
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number is the PHY signal in the order RX0, TX0, TX1, RX1.
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unevaluatedProperties: false
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properties:
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# Static lane mappings are mutually exclusive with typec-mux/orientation-mux
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data-lanes:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 2
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oneOf:
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- items: # USB3, normal orientation
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- const: 1
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- const: 0
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- items: # USB3, flipped orientation
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- const: 2
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- const: 3
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required:
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- data-lanes
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port@1:
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$ref: /schemas/graph.yaml#/properties/port

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