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miquelraynalmiquelraynal
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mtd: spinand: Create an array of operation templates
Currently, the SPI NAND core implementation directly calls macros to get the various operations in shape. These macros are specific to the bus interface, currently only supporting the single SDR interface (any command following the 1S-XX-XX pattern). Introducing support for other bus interfaces (such as octal DTR) would mean that every user of these macros should become aware of the current bus interface and act accordingly, picking up and adapting to the current configuration. This would add quite a bit of boilerplate, be repetitive as well as error prone in case we miss one occurrence. Instead, let's create a table with all SPI NAND memory operations that are currently supported. We initialize them with the same single SDR _OP macros as before. This opens the possibility for users of the individual macros to make use of these templates instead. This way, when we will add another bus interface, we can just switch to another set of templates and all users will magically fill in their spi_mem_op structures with the correct ops. The existing read, write and update cache variants are also moved in this template array, which is barely noticeable by callers as we also add a structure member pointing to it. Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
1 parent c0ba929 commit 4080150

3 files changed

Lines changed: 64 additions & 21 deletions

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‎drivers/mtd/nand/spi/core.c‎

Lines changed: 28 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -184,9 +184,9 @@ static int spinand_init_quad_enable(struct spinand_device *spinand)
184184
if (!(spinand->flags & SPINAND_HAS_QE_BIT))
185185
return 0;
186186

187-
if (spinand->op_templates.read_cache->data.buswidth == 4 ||
188-
spinand->op_templates.write_cache->data.buswidth == 4 ||
189-
spinand->op_templates.update_cache->data.buswidth == 4)
187+
if (spinand->op_templates->read_cache->data.buswidth == 4 ||
188+
spinand->op_templates->write_cache->data.buswidth == 4 ||
189+
spinand->op_templates->update_cache->data.buswidth == 4)
190190
enable = true;
191191

192192
return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE,
@@ -1154,15 +1154,15 @@ static int spinand_create_dirmap(struct spinand_device *spinand,
11541154
info.offset = plane << fls(nand->memorg.pagesize);
11551155

11561156
info.length = nanddev_page_size(nand) + nanddev_per_page_oobsize(nand);
1157-
info.op_tmpl = *spinand->op_templates.update_cache;
1157+
info.op_tmpl = *spinand->op_templates->update_cache;
11581158
desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
11591159
spinand->spimem, &info);
11601160
if (IS_ERR(desc))
11611161
return PTR_ERR(desc);
11621162

11631163
spinand->dirmaps[plane].wdesc = desc;
11641164

1165-
info.op_tmpl = *spinand->op_templates.read_cache;
1165+
info.op_tmpl = *spinand->op_templates->read_cache;
11661166
desc = spinand_create_rdesc(spinand, &info);
11671167
if (IS_ERR(desc))
11681168
return PTR_ERR(desc);
@@ -1177,7 +1177,7 @@ static int spinand_create_dirmap(struct spinand_device *spinand,
11771177
}
11781178

11791179
info.length = nanddev_page_size(nand) + nanddev_per_page_oobsize(nand);
1180-
info.op_tmpl = *spinand->op_templates.update_cache;
1180+
info.op_tmpl = *spinand->op_templates->update_cache;
11811181
info.op_tmpl.data.ecc = true;
11821182
desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
11831183
spinand->spimem, &info);
@@ -1186,7 +1186,7 @@ static int spinand_create_dirmap(struct spinand_device *spinand,
11861186

11871187
spinand->dirmaps[plane].wdesc_ecc = desc;
11881188

1189-
info.op_tmpl = *spinand->op_templates.read_cache;
1189+
info.op_tmpl = *spinand->op_templates->read_cache;
11901190
info.op_tmpl.data.ecc = true;
11911191
desc = spinand_create_rdesc(spinand, &info);
11921192
if (IS_ERR(desc))
@@ -1324,6 +1324,22 @@ static void spinand_manufacturer_cleanup(struct spinand_device *spinand)
13241324
return spinand->manufacturer->ops->cleanup(spinand);
13251325
}
13261326

1327+
static void spinand_init_ssdr_templates(struct spinand_device *spinand)
1328+
{
1329+
struct spinand_mem_ops *tmpl = &spinand->ssdr_op_templates;
1330+
1331+
tmpl->reset = (struct spi_mem_op)SPINAND_RESET_1S_0_0_OP;
1332+
tmpl->readid = (struct spi_mem_op)SPINAND_READID_1S_1S_1S_OP(0, 0, NULL, 0);
1333+
tmpl->wr_en = (struct spi_mem_op)SPINAND_WR_EN_1S_0_0_OP;
1334+
tmpl->wr_dis = (struct spi_mem_op)SPINAND_WR_DIS_1S_0_0_OP;
1335+
tmpl->set_feature = (struct spi_mem_op)SPINAND_SET_FEATURE_1S_1S_1S_OP(0, NULL);
1336+
tmpl->get_feature = (struct spi_mem_op)SPINAND_GET_FEATURE_1S_1S_1S_OP(0, NULL);
1337+
tmpl->blk_erase = (struct spi_mem_op)SPINAND_BLK_ERASE_1S_1S_0_OP(0);
1338+
tmpl->page_read = (struct spi_mem_op)SPINAND_PAGE_READ_1S_1S_0_OP(0);
1339+
tmpl->prog_exec = (struct spi_mem_op)SPINAND_PROG_EXEC_1S_1S_0_OP(0);
1340+
spinand->op_templates = &spinand->ssdr_op_templates;
1341+
}
1342+
13271343
static const struct spi_mem_op *
13281344
spinand_select_op_variant(struct spinand_device *spinand,
13291345
const struct spinand_op_variants *variants)
@@ -1419,21 +1435,21 @@ int spinand_match_and_init(struct spinand_device *spinand,
14191435
if (!op)
14201436
return -EOPNOTSUPP;
14211437

1422-
spinand->op_templates.read_cache = op;
1438+
spinand->ssdr_op_templates.read_cache = op;
14231439

14241440
op = spinand_select_op_variant(spinand,
14251441
info->op_variants.write_cache);
14261442
if (!op)
14271443
return -EOPNOTSUPP;
14281444

1429-
spinand->op_templates.write_cache = op;
1445+
spinand->ssdr_op_templates.write_cache = op;
14301446

14311447
op = spinand_select_op_variant(spinand,
14321448
info->op_variants.update_cache);
14331449
if (!op)
14341450
return -EOPNOTSUPP;
14351451

1436-
spinand->op_templates.update_cache = op;
1452+
spinand->ssdr_op_templates.update_cache = op;
14371453

14381454
return 0;
14391455
}
@@ -1548,6 +1564,8 @@ static int spinand_init(struct spinand_device *spinand)
15481564
if (!spinand->scratchbuf)
15491565
return -ENOMEM;
15501566

1567+
spinand_init_ssdr_templates(spinand);
1568+
15511569
ret = spinand_detect(spinand);
15521570
if (ret)
15531571
goto err_free_bufs;

‎drivers/mtd/nand/spi/winbond.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -291,7 +291,7 @@ static int w25n0xjw_hs_cfg(struct spinand_device *spinand)
291291
u8 sr4;
292292
int ret;
293293

294-
op = spinand->op_templates.read_cache;
294+
op = spinand->op_templates->read_cache;
295295
if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
296296
hs = false;
297297
else if (op->cmd.buswidth == 1 && op->addr.buswidth == 1 &&
@@ -355,7 +355,7 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spinand)
355355
u8 io_mode;
356356
int ret;
357357

358-
op = spinand->op_templates.read_cache;
358+
op = spinand->op_templates->read_cache;
359359

360360
single = (op->cmd.buswidth == 1 && op->addr.buswidth == 1 && op->data.buswidth == 1);
361361
dtr = (op->cmd.dtr || op->addr.dtr || op->data.dtr);

‎include/linux/mtd/spinand.h‎

Lines changed: 34 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -600,17 +600,45 @@ struct spinand_dirmap {
600600
struct spi_mem_dirmap_desc *rdesc_ecc;
601601
};
602602

603+
/**
604+
* struct spinand_mem_ops - SPI NAND memory operations
605+
* @reset: reset op template
606+
* @readid: read ID op template
607+
* @wr_en: write enable op template
608+
* @wr_dis: write disable op template
609+
* @set_feature: set feature op template
610+
* @get_feature: get feature op template
611+
* @blk_erase: blk erase op template
612+
* @page_read: page read op template
613+
* @prog_exec: prog exec op template
614+
* @read_cache: read cache op template
615+
* @write_cache: write cache op template
616+
* @update_cache: update cache op template
617+
*/
618+
struct spinand_mem_ops {
619+
struct spi_mem_op reset;
620+
struct spi_mem_op readid;
621+
struct spi_mem_op wr_en;
622+
struct spi_mem_op wr_dis;
623+
struct spi_mem_op set_feature;
624+
struct spi_mem_op get_feature;
625+
struct spi_mem_op blk_erase;
626+
struct spi_mem_op page_read;
627+
struct spi_mem_op prog_exec;
628+
const struct spi_mem_op *read_cache;
629+
const struct spi_mem_op *write_cache;
630+
const struct spi_mem_op *update_cache;
631+
};
632+
603633
/**
604634
* struct spinand_device - SPI NAND device instance
605635
* @base: NAND device instance
606636
* @spimem: pointer to the SPI mem object
607637
* @lock: lock used to serialize accesses to the NAND
608638
* @id: NAND ID as returned by READ_ID
609639
* @flags: NAND flags
610-
* @op_templates: various SPI mem op templates
611-
* @op_templates.read_cache: read cache op template
612-
* @op_templates.write_cache: write cache op template
613-
* @op_templates.update_cache: update cache op template
640+
* @ssdr_op_templates: Templates for all single SDR SPI mem operations
641+
* @op_templates: Templates for all SPI mem operations
614642
* @select_target: select a specific target/die. Usually called before sending
615643
* a command addressing a page or an eraseblock embedded in
616644
* this die. Only required if your chip exposes several dies
@@ -644,11 +672,8 @@ struct spinand_device {
644672
struct spinand_id id;
645673
u32 flags;
646674

647-
struct {
648-
const struct spi_mem_op *read_cache;
649-
const struct spi_mem_op *write_cache;
650-
const struct spi_mem_op *update_cache;
651-
} op_templates;
675+
struct spinand_mem_ops ssdr_op_templates;
676+
struct spinand_mem_ops *op_templates;
652677

653678
struct spinand_dirmap *dirmaps;
654679

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