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Lucas De Marchi
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drm/i915/gem: replace IS_GEN and friends with GRAPHICS_VER
This was done by the following semantic patch: @@ expression i915; @@ - INTEL_GEN(i915) + GRAPHICS_VER(i915) @@ expression i915; expression E; @@ - INTEL_GEN(i915) >= E + GRAPHICS_VER(i915) >= E @@ expression dev_priv; expression E; @@ - !IS_GEN(dev_priv, E) + GRAPHICS_VER(dev_priv) != E @@ expression dev_priv; expression E; @@ - IS_GEN(dev_priv, E) + GRAPHICS_VER(dev_priv) == E @@ expression dev_priv; expression from, until; @@ - IS_GEN_RANGE(dev_priv, from, until) + IS_GRAPHICS_VER(dev_priv, from, until) @def@ expression E; identifier id =~ "^gen$"; @@ - id = GRAPHICS_VER(E) + ver = GRAPHICS_VER(E) @@ identifier def.id; @@ - id + ver It also takes care of renaming the variable we assign to GRAPHICS_VER() so to use "ver" rather than "gen". Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210605155356.4183026-4-lucas.demarchi@intel.com
1 parent fa20cbd commit 40e1956

11 files changed

Lines changed: 54 additions & 54 deletions

‎drivers/gpu/drm/i915/gem/i915_gem_context.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1190,7 +1190,7 @@ static void set_ppgtt_barrier(void *data)
11901190
{
11911191
struct i915_address_space *old = data;
11921192

1193-
if (INTEL_GEN(old->i915) < 8)
1193+
if (GRAPHICS_VER(old->i915) < 8)
11941194
gen6_ppgtt_unpin_all(i915_vm_to_ppgtt(old));
11951195

11961196
i915_vm_close(old);
@@ -1436,7 +1436,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
14361436
context->max_eus_per_subslice = user->max_eus_per_subslice;
14371437

14381438
/* Part specific restrictions. */
1439-
if (IS_GEN(i915, 11)) {
1439+
if (GRAPHICS_VER(i915) == 11) {
14401440
unsigned int hw_s = hweight8(device->slice_mask);
14411441
unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
14421442
unsigned int req_s = hweight8(context->slice_mask);
@@ -1503,7 +1503,7 @@ static int set_sseu(struct i915_gem_context *ctx,
15031503
if (args->size < sizeof(user_sseu))
15041504
return -EINVAL;
15051505

1506-
if (!IS_GEN(i915, 11))
1506+
if (GRAPHICS_VER(i915) != 11)
15071507
return -ENODEV;
15081508

15091509
if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),

‎drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -500,7 +500,7 @@ eb_validate_vma(struct i915_execbuffer *eb,
500500
* also covers all platforms with local memory.
501501
*/
502502
if (entry->relocation_count &&
503-
INTEL_GEN(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
503+
GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
504504
return -EINVAL;
505505

506506
if (unlikely(entry->flags & eb->invalid_flags))
@@ -1439,7 +1439,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
14391439

14401440
static bool reloc_can_use_engine(const struct intel_engine_cs *engine)
14411441
{
1442-
return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6);
1442+
return engine->class != VIDEO_DECODE_CLASS || GRAPHICS_VER(engine->i915) != 6;
14431443
}
14441444

14451445
static u32 *reloc_gpu(struct i915_execbuffer *eb,
@@ -1671,7 +1671,7 @@ eb_relocate_entry(struct i915_execbuffer *eb,
16711671
* batchbuffers.
16721672
*/
16731673
if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
1674-
IS_GEN(eb->i915, 6)) {
1674+
GRAPHICS_VER(eb->i915) == 6) {
16751675
err = i915_vma_bind(target->vma,
16761676
target->vma->obj->cache_level,
16771677
PIN_GLOBAL, NULL);
@@ -2332,7 +2332,7 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
23322332
u32 *cs;
23332333
int i;
23342334

2335-
if (!IS_GEN(rq->engine->i915, 7) || rq->engine->id != RCS0) {
2335+
if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) {
23362336
drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");
23372337
return -EINVAL;
23382338
}
@@ -3375,7 +3375,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
33753375

33763376
eb.batch_flags = 0;
33773377
if (args->flags & I915_EXEC_SECURE) {
3378-
if (INTEL_GEN(i915) >= 11)
3378+
if (GRAPHICS_VER(i915) >= 11)
33793379
return -ENODEV;
33803380

33813381
/* Return -EPERM to trigger fallback code on old binaries. */

‎drivers/gpu/drm/i915/gem/i915_gem_mman.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
6464
/* mmap ioctl is disallowed for all platforms after TGL-LP. This also
6565
* covers all platforms with local memory.
6666
*/
67-
if (INTEL_GEN(i915) >= 12 && !IS_TIGERLAKE(i915))
67+
if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915))
6868
return -EOPNOTSUPP;
6969

7070
if (args->flags & ~(I915_MMAP_WC))

‎drivers/gpu/drm/i915/gem/i915_gem_object_blt.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
7272

7373
GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
7474

75-
if (INTEL_GEN(i915) >= 8) {
75+
if (GRAPHICS_VER(i915) >= 8) {
7676
*cmd++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7 - 2);
7777
*cmd++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
7878
*cmd++ = 0;
@@ -232,7 +232,7 @@ static bool wa_1209644611_applies(struct drm_i915_private *i915, u32 size)
232232
{
233233
u32 height = size >> PAGE_SHIFT;
234234

235-
if (!IS_GEN(i915, 11))
235+
if (GRAPHICS_VER(i915) != 11)
236236
return false;
237237

238238
return height % 4 == 3 && height <= 8;
@@ -297,7 +297,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce,
297297
size = min_t(u64, rem, block_size);
298298
GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
299299

300-
if (INTEL_GEN(i915) >= 9 &&
300+
if (GRAPHICS_VER(i915) >= 9 &&
301301
!wa_1209644611_applies(i915, size)) {
302302
*cmd++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2);
303303
*cmd++ = BLT_DEPTH_32 | PAGE_SIZE;
@@ -309,7 +309,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce,
309309
*cmd++ = PAGE_SIZE;
310310
*cmd++ = lower_32_bits(src_offset);
311311
*cmd++ = upper_32_bits(src_offset);
312-
} else if (INTEL_GEN(i915) >= 8) {
312+
} else if (GRAPHICS_VER(i915) >= 8) {
313313
*cmd++ = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (10 - 2);
314314
*cmd++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
315315
*cmd++ = 0;

‎drivers/gpu/drm/i915/gem/i915_gem_stolen.c‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *i915,
3838
return -ENODEV;
3939

4040
/* WaSkipStolenMemoryFirstPage:bdw+ */
41-
if (INTEL_GEN(i915) >= 8 && start < 4096)
41+
if (GRAPHICS_VER(i915) >= 8 && start < 4096)
4242
start = 4096;
4343

4444
mutex_lock(&i915->mm.stolen_lock);
@@ -84,14 +84,14 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
8484
*/
8585

8686
/* Make sure we don't clobber the GTT if it's within stolen memory */
87-
if (INTEL_GEN(i915) <= 4 &&
87+
if (GRAPHICS_VER(i915) <= 4 &&
8888
!IS_G33(i915) && !IS_PINEVIEW(i915) && !IS_G4X(i915)) {
8989
struct resource stolen[2] = {*dsm, *dsm};
9090
struct resource ggtt_res;
9191
resource_size_t ggtt_start;
9292

9393
ggtt_start = intel_uncore_read(uncore, PGTBL_CTL);
94-
if (IS_GEN(i915, 4))
94+
if (GRAPHICS_VER(i915) == 4)
9595
ggtt_start = (ggtt_start & PGTBL_ADDRESS_LO_MASK) |
9696
(ggtt_start & PGTBL_ADDRESS_HI_MASK) << 28;
9797
else
@@ -156,7 +156,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
156156
* GEN3 firmware likes to smash pci bridges into the stolen
157157
* range. Apparently this works.
158158
*/
159-
if (!r && !IS_GEN(i915, 3)) {
159+
if (!r && GRAPHICS_VER(i915) != 3) {
160160
drm_err(&i915->drm,
161161
"conflict detected with stolen region: %pR\n",
162162
dsm);
@@ -197,7 +197,7 @@ static void g4x_get_stolen_reserved(struct drm_i915_private *i915,
197197
* Whether ILK really reuses the ELK register for this is unclear.
198198
* Let's see if we catch anyone with this supposedly enabled on ILK.
199199
*/
200-
drm_WARN(&i915->drm, IS_GEN(i915, 5),
200+
drm_WARN(&i915->drm, GRAPHICS_VER(i915) == 5,
201201
"ILK stolen reserved found? 0x%08x\n",
202202
reg_val);
203203

@@ -399,7 +399,7 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
399399
return 0;
400400
}
401401

402-
if (intel_vtd_active() && INTEL_GEN(i915) < 8) {
402+
if (intel_vtd_active() && GRAPHICS_VER(i915) < 8) {
403403
drm_notice(&i915->drm,
404404
"%s, disabling use of stolen memory\n",
405405
"DMAR active");
@@ -421,7 +421,7 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
421421
reserved_base = stolen_top;
422422
reserved_size = 0;
423423

424-
switch (INTEL_GEN(i915)) {
424+
switch (GRAPHICS_VER(i915)) {
425425
case 2:
426426
case 3:
427427
break;
@@ -456,7 +456,7 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
456456
&reserved_base, &reserved_size);
457457
break;
458458
default:
459-
MISSING_CASE(INTEL_GEN(i915));
459+
MISSING_CASE(GRAPHICS_VER(i915));
460460
fallthrough;
461461
case 11:
462462
case 12:

‎drivers/gpu/drm/i915/gem/i915_gem_tiling.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -62,14 +62,14 @@ u32 i915_gem_fence_size(struct drm_i915_private *i915,
6262

6363
GEM_BUG_ON(!stride);
6464

65-
if (INTEL_GEN(i915) >= 4) {
65+
if (GRAPHICS_VER(i915) >= 4) {
6666
stride *= i915_gem_tile_height(tiling);
6767
GEM_BUG_ON(!IS_ALIGNED(stride, I965_FENCE_PAGE));
6868
return roundup(size, stride);
6969
}
7070

7171
/* Previous chips need a power-of-two fence region when tiling */
72-
if (IS_GEN(i915, 3))
72+
if (GRAPHICS_VER(i915) == 3)
7373
ggtt_size = 1024*1024;
7474
else
7575
ggtt_size = 512*1024;
@@ -102,7 +102,7 @@ u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
102102
if (tiling == I915_TILING_NONE)
103103
return I915_GTT_MIN_ALIGNMENT;
104104

105-
if (INTEL_GEN(i915) >= 4)
105+
if (GRAPHICS_VER(i915) >= 4)
106106
return I965_FENCE_PAGE;
107107

108108
/*
@@ -130,10 +130,10 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
130130
/* check maximum stride & object size */
131131
/* i965+ stores the end address of the gtt mapping in the fence
132132
* reg, so dont bother to check the size */
133-
if (INTEL_GEN(i915) >= 7) {
133+
if (GRAPHICS_VER(i915) >= 7) {
134134
if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
135135
return false;
136-
} else if (INTEL_GEN(i915) >= 4) {
136+
} else if (GRAPHICS_VER(i915) >= 4) {
137137
if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
138138
return false;
139139
} else {
@@ -144,7 +144,7 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
144144
return false;
145145
}
146146

147-
if (IS_GEN(i915, 2) ||
147+
if (GRAPHICS_VER(i915) == 2 ||
148148
(tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
149149
tile_width = 128;
150150
else

‎drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -152,8 +152,8 @@ static int prepare_blit(const struct tiled_blits *t,
152152
struct blit_buffer *src,
153153
struct drm_i915_gem_object *batch)
154154
{
155-
const int gen = INTEL_GEN(to_i915(batch->base.dev));
156-
bool use_64b_reloc = gen >= 8;
155+
const int ver = GRAPHICS_VER(to_i915(batch->base.dev));
156+
bool use_64b_reloc = ver >= 8;
157157
u32 src_pitch, dst_pitch;
158158
u32 cmd, *cs;
159159

@@ -171,15 +171,15 @@ static int prepare_blit(const struct tiled_blits *t,
171171
*cs++ = cmd;
172172

173173
cmd = MI_FLUSH_DW;
174-
if (gen >= 8)
174+
if (ver >= 8)
175175
cmd++;
176176
*cs++ = cmd;
177177
*cs++ = 0;
178178
*cs++ = 0;
179179
*cs++ = 0;
180180

181181
cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
182-
if (gen >= 8)
182+
if (ver >= 8)
183183
cmd += 2;
184184

185185
src_pitch = t->width * 4;
@@ -666,7 +666,7 @@ static int igt_client_tiled_blits(void *arg)
666666
int inst = 0;
667667

668668
/* Test requires explicit BLT tiling controls */
669-
if (INTEL_GEN(i915) < 4)
669+
if (GRAPHICS_VER(i915) < 4)
670670
return 0;
671671

672672
if (bad_swizzling(i915)) /* Requires sane (sub-page) swizzling */

‎drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -221,12 +221,12 @@ static int gpu_set(struct context *ctx, unsigned long offset, u32 v)
221221
goto out_rq;
222222
}
223223

224-
if (INTEL_GEN(ctx->engine->i915) >= 8) {
224+
if (GRAPHICS_VER(ctx->engine->i915) >= 8) {
225225
*cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
226226
*cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset);
227227
*cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);
228228
*cs++ = v;
229-
} else if (INTEL_GEN(ctx->engine->i915) >= 4) {
229+
} else if (GRAPHICS_VER(ctx->engine->i915) >= 4) {
230230
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
231231
*cs++ = 0;
232232
*cs++ = i915_ggtt_offset(vma) + offset;

‎drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -897,7 +897,7 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v
897897
{
898898
u32 *cmd;
899899

900-
GEM_BUG_ON(INTEL_GEN(vma->vm->i915) < 8);
900+
GEM_BUG_ON(GRAPHICS_VER(vma->vm->i915) < 8);
901901

902902
cmd = i915_gem_object_pin_map(rpcs, I915_MAP_WB);
903903
if (IS_ERR(cmd))
@@ -932,7 +932,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
932932

933933
GEM_BUG_ON(!intel_engine_can_store_dword(ce->engine));
934934

935-
if (INTEL_GEN(i915) < 8)
935+
if (GRAPHICS_VER(i915) < 8)
936936
return -EINVAL;
937937

938938
vma = i915_vma_instance(obj, ce->vm, NULL);
@@ -1100,7 +1100,7 @@ __read_slice_count(struct intel_context *ce,
11001100
return ret;
11011101
}
11021102

1103-
if (INTEL_GEN(ce->engine->i915) >= 11) {
1103+
if (GRAPHICS_VER(ce->engine->i915) >= 11) {
11041104
s_mask = GEN11_RPCS_S_CNT_MASK;
11051105
s_shift = GEN11_RPCS_S_CNT_SHIFT;
11061106
} else {
@@ -1229,7 +1229,7 @@ __igt_ctx_sseu(struct drm_i915_private *i915,
12291229
int inst = 0;
12301230
int ret = 0;
12311231

1232-
if (INTEL_GEN(i915) < 9)
1232+
if (GRAPHICS_VER(i915) < 9)
12331233
return 0;
12341234

12351235
if (flags & TEST_RESET)
@@ -1518,7 +1518,7 @@ static int write_to_scratch(struct i915_gem_context *ctx,
15181518
}
15191519

15201520
*cmd++ = MI_STORE_DWORD_IMM_GEN4;
1521-
if (INTEL_GEN(i915) >= 8) {
1521+
if (GRAPHICS_VER(i915) >= 8) {
15221522
*cmd++ = lower_32_bits(offset);
15231523
*cmd++ = upper_32_bits(offset);
15241524
} else {
@@ -1608,7 +1608,7 @@ static int read_from_scratch(struct i915_gem_context *ctx,
16081608
if (IS_ERR(obj))
16091609
return PTR_ERR(obj);
16101610

1611-
if (INTEL_GEN(i915) >= 8) {
1611+
if (GRAPHICS_VER(i915) >= 8) {
16121612
const u32 GPR0 = engine->mmio_base + 0x600;
16131613

16141614
vm = i915_gem_context_get_vm_rcu(ctx);
@@ -1776,7 +1776,7 @@ static int igt_vm_isolation(void *arg)
17761776
u32 expected;
17771777
int err;
17781778

1779-
if (INTEL_GEN(i915) < 7)
1779+
if (GRAPHICS_VER(i915) < 7)
17801780
return 0;
17811781

17821782
/*
@@ -1830,7 +1830,7 @@ static int igt_vm_isolation(void *arg)
18301830
continue;
18311831

18321832
/* Not all engines have their own GPR! */
1833-
if (INTEL_GEN(i915) < 8 && engine->class != RENDER_CLASS)
1833+
if (GRAPHICS_VER(i915) < 8 && engine->class != RENDER_CLASS)
18341834
continue;
18351835

18361836
while (!__igt_timeout(end_time, NULL)) {

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