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Commit 40f1171

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Ben Skeggs
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drm/nouveau/fence: use NVIDIA's headers for sync()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
1 parent 60cdada commit 40f1171

5 files changed

Lines changed: 39 additions & 36 deletions

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‎drivers/gpu/drm/nouveau/include/nvhw/class/cl176e.h‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
/* SPDX-License-Identifier: MIT */
2+
#ifndef _cl176e_h_
3+
#define _cl176e_h_
4+
5+
#define NV176E_SET_OBJECT (0x00000000)
6+
#define NV176E_SET_CONTEXT_DMA_SEMAPHORE (0x00000060)
7+
#define NV176E_SEMAPHORE_OFFSET (0x00000064)
8+
#define NV176E_SEMAPHORE_ACQUIRE (0x00000068)
9+
#define NV176E_SEMAPHORE_RELEASE (0x0000006c)
10+
#endif

‎drivers/gpu/drm/nouveau/nouveau_dma.h‎

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -103,20 +103,6 @@ WIND_RING(struct nouveau_channel *chan)
103103
chan->dma.cur = chan->dma.put;
104104
}
105105

106-
/* FIFO methods */
107-
#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010
108-
#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014
109-
#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018
110-
#define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c
111-
#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001
112-
#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002
113-
#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004
114-
#define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000
115-
#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
116-
#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
117-
#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
118-
#define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c
119-
120106
/* NV_SW object class */
121107
#define NV_SW_DMA_VBLSEM 0x0000018c
122108
#define NV_SW_VBLSEM_OFFSET 0x00000400

‎drivers/gpu/drm/nouveau/nv17_fence.c‎

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,8 @@
3030
#include <nvif/class.h>
3131
#include <nvif/cl0002.h>
3232

33+
#include <nvhw/class/cl176e.h>
34+
3335
int
3436
nv17_fence_sync(struct nouveau_fence *fence,
3537
struct nouveau_channel *prev, struct nouveau_channel *chan)
@@ -52,18 +54,18 @@ nv17_fence_sync(struct nouveau_fence *fence,
5254

5355
ret = PUSH_WAIT(ppush, 5);
5456
if (!ret) {
55-
PUSH_NVSQ(ppush, NV176E, NV11_SUBCHAN_DMA_SEMAPHORE, fctx->sema.handle,
56-
NV11_SUBCHAN_SEMAPHORE_OFFSET, 0,
57-
NV11_SUBCHAN_SEMAPHORE_ACQUIRE, value + 0,
58-
NV11_SUBCHAN_SEMAPHORE_RELEASE, value + 1);
57+
PUSH_MTHD(ppush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle,
58+
SEMAPHORE_OFFSET, 0,
59+
SEMAPHORE_ACQUIRE, value + 0,
60+
SEMAPHORE_RELEASE, value + 1);
5961
PUSH_KICK(ppush);
6062
}
6163

6264
if (!ret && !(ret = PUSH_WAIT(npush, 5))) {
63-
PUSH_NVSQ(npush, NV176E, NV11_SUBCHAN_DMA_SEMAPHORE, fctx->sema.handle,
64-
NV11_SUBCHAN_SEMAPHORE_OFFSET, 0,
65-
NV11_SUBCHAN_SEMAPHORE_ACQUIRE, value + 1,
66-
NV11_SUBCHAN_SEMAPHORE_RELEASE, value + 2);
65+
PUSH_MTHD(npush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle,
66+
SEMAPHORE_OFFSET, 0,
67+
SEMAPHORE_ACQUIRE, value + 1,
68+
SEMAPHORE_RELEASE, value + 2);
6769
PUSH_KICK(npush);
6870
}
6971

‎drivers/gpu/drm/nouveau/nv84_fence.c‎

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -61,13 +61,16 @@ nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
6161
struct nvif_push *push = chan->chan.push;
6262
int ret = PUSH_WAIT(push, 7);
6363
if (ret == 0) {
64-
PUSH_NVSQ(push, NV826F, NV11_SUBCHAN_DMA_SEMAPHORE, chan->vram.handle);
65-
PUSH_NVSQ(push, NV826F,
66-
NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual),
67-
NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual),
68-
NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence,
69-
NV84_SUBCHAN_SEMAPHORE_TRIGGER,
70-
NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
64+
PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
65+
66+
PUSH_MTHD(push, NV826F, SEMAPHOREA,
67+
NVVAL(NV826F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)),
68+
69+
SEMAPHOREB, lower_32_bits(virtual),
70+
SEMAPHOREC, sequence,
71+
72+
SEMAPHORED,
73+
NVDEF(NV826F, SEMAPHORED, OPERATION, ACQ_GEQ));
7174
PUSH_KICK(push);
7275
}
7376
return ret;

‎drivers/gpu/drm/nouveau/nvc0_fence.c‎

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -60,13 +60,15 @@ nvc0_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
6060
struct nvif_push *push = chan->chan.push;
6161
int ret = PUSH_WAIT(push, 5);
6262
if (ret == 0) {
63-
PUSH_NVSQ(push, NV906F,
64-
NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual),
65-
NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual),
66-
NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence,
67-
NV84_SUBCHAN_SEMAPHORE_TRIGGER,
68-
NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL |
69-
NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
63+
PUSH_MTHD(push, NV906F, SEMAPHOREA,
64+
NVVAL(NV906F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)),
65+
66+
SEMAPHOREB, lower_32_bits(virtual),
67+
SEMAPHOREC, sequence,
68+
69+
SEMAPHORED,
70+
NVDEF(NV906F, SEMAPHORED, OPERATION, ACQ_GEQ) |
71+
NVDEF(NV906F, SEMAPHORED, ACQUIRE_SWITCH, ENABLED));
7072
PUSH_KICK(push);
7173
}
7274
return ret;

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