@@ -300,7 +300,9 @@ int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev,
300300 queue_input .mqd_addr = amdgpu_bo_gpu_offset (ring -> mqd_obj );
301301 queue_input .wptr_addr = ring -> wptr_gpu_addr ;
302302
303+ amdgpu_mes_lock (& adev -> mes );
303304 r = adev -> mes .funcs -> map_legacy_queue (& adev -> mes , & queue_input );
305+ amdgpu_mes_unlock (& adev -> mes );
304306 if (r )
305307 DRM_ERROR ("failed to map legacy queue\n" );
306308
@@ -323,7 +325,9 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
323325 queue_input .trail_fence_addr = gpu_addr ;
324326 queue_input .trail_fence_data = seq ;
325327
328+ amdgpu_mes_lock (& adev -> mes );
326329 r = adev -> mes .funcs -> unmap_legacy_queue (& adev -> mes , & queue_input );
330+ amdgpu_mes_unlock (& adev -> mes );
327331 if (r )
328332 DRM_ERROR ("failed to unmap legacy queue\n" );
329333
@@ -353,7 +357,9 @@ int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,
353357 if (ring -> funcs -> type == AMDGPU_RING_TYPE_GFX )
354358 queue_input .legacy_gfx = true;
355359
360+ amdgpu_mes_lock (& adev -> mes );
356361 r = adev -> mes .funcs -> reset_hw_queue (& adev -> mes , & queue_input );
362+ amdgpu_mes_unlock (& adev -> mes );
357363 if (r )
358364 DRM_ERROR ("failed to reset legacy queue\n" );
359365
@@ -383,7 +389,9 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg)
383389 goto error ;
384390 }
385391
392+ amdgpu_mes_lock (& adev -> mes );
386393 r = adev -> mes .funcs -> misc_op (& adev -> mes , & op_input );
394+ amdgpu_mes_unlock (& adev -> mes );
387395 if (r )
388396 dev_err (adev -> dev , "failed to read reg (0x%x)\n" , reg );
389397 else
@@ -411,7 +419,9 @@ int amdgpu_mes_wreg(struct amdgpu_device *adev,
411419 goto error ;
412420 }
413421
422+ amdgpu_mes_lock (& adev -> mes );
414423 r = adev -> mes .funcs -> misc_op (& adev -> mes , & op_input );
424+ amdgpu_mes_unlock (& adev -> mes );
415425 if (r )
416426 dev_err (adev -> dev , "failed to write reg (0x%x)\n" , reg );
417427
@@ -438,7 +448,9 @@ int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
438448 goto error ;
439449 }
440450
451+ amdgpu_mes_lock (& adev -> mes );
441452 r = adev -> mes .funcs -> misc_op (& adev -> mes , & op_input );
453+ amdgpu_mes_unlock (& adev -> mes );
442454 if (r )
443455 dev_err (adev -> dev , "failed to reg_write_reg_wait\n" );
444456
@@ -463,7 +475,9 @@ int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,
463475 goto error ;
464476 }
465477
478+ amdgpu_mes_lock (& adev -> mes );
466479 r = adev -> mes .funcs -> misc_op (& adev -> mes , & op_input );
480+ amdgpu_mes_unlock (& adev -> mes );
467481 if (r )
468482 dev_err (adev -> dev , "failed to reg_write_reg_wait\n" );
469483
@@ -694,7 +708,9 @@ static int amdgpu_mes_set_enforce_isolation(struct amdgpu_device *adev,
694708 goto error ;
695709 }
696710
711+ amdgpu_mes_lock (& adev -> mes );
697712 r = adev -> mes .funcs -> misc_op (& adev -> mes , & op_input );
713+ amdgpu_mes_unlock (& adev -> mes );
698714 if (r )
699715 dev_err (adev -> dev , "failed to change_config.\n" );
700716
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