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docularxuYixun Lan
docularxu
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Yixun Lan
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riscv: dts: spacemit: k1: Add "b" ISA extension
"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update k1.dtsi to conform to this rule. Signed-off-by: Guodong Xu <guodong@riscstar.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-4-254dd61cf947@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
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Lines changed: 16 additions & 16 deletions

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  • arch/riscv/boot/dts/spacemit

‎arch/riscv/boot/dts/spacemit/k1.dtsi‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -54,9 +54,9 @@
5454
compatible = "spacemit,x60", "riscv";
5555
device_type = "cpu";
5656
reg = <0>;
57-
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
57+
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
5858
riscv,isa-base = "rv64i";
59-
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
59+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
6060
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
6161
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
6262
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -84,9 +84,9 @@
8484
compatible = "spacemit,x60", "riscv";
8585
device_type = "cpu";
8686
reg = <1>;
87-
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
87+
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
8888
riscv,isa-base = "rv64i";
89-
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
89+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
9090
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
9191
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
9292
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -114,9 +114,9 @@
114114
compatible = "spacemit,x60", "riscv";
115115
device_type = "cpu";
116116
reg = <2>;
117-
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
117+
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
118118
riscv,isa-base = "rv64i";
119-
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
119+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
120120
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
121121
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
122122
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -144,9 +144,9 @@
144144
compatible = "spacemit,x60", "riscv";
145145
device_type = "cpu";
146146
reg = <3>;
147-
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
147+
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
148148
riscv,isa-base = "rv64i";
149-
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
149+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
150150
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
151151
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
152152
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -174,9 +174,9 @@
174174
compatible = "spacemit,x60", "riscv";
175175
device_type = "cpu";
176176
reg = <4>;
177-
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
177+
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
178178
riscv,isa-base = "rv64i";
179-
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
179+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
180180
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
181181
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
182182
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -204,9 +204,9 @@
204204
compatible = "spacemit,x60", "riscv";
205205
device_type = "cpu";
206206
reg = <5>;
207-
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
207+
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
208208
riscv,isa-base = "rv64i";
209-
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
209+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
210210
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
211211
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
212212
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -234,9 +234,9 @@
234234
compatible = "spacemit,x60", "riscv";
235235
device_type = "cpu";
236236
reg = <6>;
237-
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
237+
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
238238
riscv,isa-base = "rv64i";
239-
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
239+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
240240
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
241241
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
242242
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -264,9 +264,9 @@
264264
compatible = "spacemit,x60", "riscv";
265265
device_type = "cpu";
266266
reg = <7>;
267-
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
267+
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
268268
riscv,isa-base = "rv64i";
269-
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
269+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
270270
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
271271
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
272272
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",

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