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Merge tag 'riscv-cache-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
RISC-V cache drivers for v6.8 The SiFive composable cache driver moves to the cache driver subdirectory from the drivers/soc and grows support for non-coherent cache operations. The immediate user for these is the jh7100 SoC, that a rake of people have on VisionFive v1 or Beagle-V Starlight boards. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-cache-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: errata: Make ERRATA_STARFIVE_JH7100 depend on !DMA_DIRECT_REMAP riscv: errata: Add StarFive JH7100 errata soc: sifive: ccache: Add StarFive JH7100 support dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible soc: sifive: shunt ccache driver to drivers/cache Link: https://lore.kernel.org/r/20231221-catatonic-monday-d4c61283b136@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents cd845df + 9a9e8d8 commit 41ab5e1

10 files changed

Lines changed: 99 additions & 26 deletions

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‎Documentation/devicetree/bindings/cache/sifive,ccache0.yaml‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,9 @@ properties:
3838
- sifive,fu740-c000-ccache
3939
- const: cache
4040
- items:
41-
- const: starfive,jh7110-ccache
41+
- enum:
42+
- starfive,jh7100-ccache
43+
- starfive,jh7110-ccache
4244
- const: sifive,ccache0
4345
- const: cache
4446
- items:
@@ -88,6 +90,7 @@ allOf:
8890
contains:
8991
enum:
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- sifive,fu740-c000-ccache
93+
- starfive,jh7100-ccache
9194
- starfive,jh7110-ccache
9295
- microchip,mpfs-ccache
9396

@@ -111,6 +114,7 @@ allOf:
111114
contains:
112115
enum:
113116
- sifive,fu740-c000-ccache
117+
- starfive,jh7100-ccache
114118
- starfive,jh7110-ccache
115119

116120
then:

‎MAINTAINERS‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -19783,6 +19783,13 @@ S: Supported
1978319783
N: sifive
1978419784
K: [^@]sifive
1978519785

19786+
SIFIVE CACHE DRIVER
19787+
M: Conor Dooley <conor@kernel.org>
19788+
L: linux-riscv@lists.infradead.org
19789+
S: Maintained
19790+
F: Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
19791+
F: drivers/cache/sifive_ccache.c
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1978619793
SIFIVE FU540 SYSTEM-ON-CHIP
1978719794
M: Paul Walmsley <paul.walmsley@sifive.com>
1978819795
M: Palmer Dabbelt <palmer@dabbelt.com>
@@ -19798,13 +19805,6 @@ S: Maintained
1979819805
F: Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
1979919806
F: drivers/dma/sf-pdma/
1980019807

19801-
SIFIVE SOC DRIVERS
19802-
M: Conor Dooley <conor@kernel.org>
19803-
L: linux-riscv@lists.infradead.org
19804-
S: Maintained
19805-
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
19806-
F: Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
19807-
F: drivers/soc/sifive/
1980819808

1980919809
SILEAD TOUCHSCREEN DRIVER
1981019810
M: Hans de Goede <hdegoede@redhat.com>

‎arch/riscv/Kconfig.errata‎

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Original file line numberDiff line numberDiff line change
@@ -53,6 +53,25 @@ config ERRATA_SIFIVE_CIP_1200
5353

5454
If you don't know what to do here, say "Y".
5555

56+
config ERRATA_STARFIVE_JH7100
57+
bool "StarFive JH7100 support"
58+
depends on ARCH_STARFIVE
59+
depends on !DMA_DIRECT_REMAP
60+
depends on NONPORTABLE
61+
select DMA_GLOBAL_POOL
62+
select RISCV_DMA_NONCOHERENT
63+
select RISCV_NONSTANDARD_CACHE_OPS
64+
select SIFIVE_CCACHE
65+
default n
66+
help
67+
The StarFive JH7100 was a test chip for the JH7110 and has
68+
caches that are non-coherent with respect to peripheral DMAs.
69+
It was designed before the Zicbom extension so needs non-standard
70+
cache operations through the SiFive cache controller.
71+
72+
Say "Y" if you want to support the BeagleV Starlight and/or
73+
StarFive VisionFive V1 boards.
74+
5675
config ERRATA_THEAD
5776
bool "T-HEAD errata"
5877
depends on RISCV_ALTERNATIVE

‎drivers/cache/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -8,4 +8,10 @@ config AX45MP_L2_CACHE
88
help
99
Support for the L2 cache controller on Andes Technology AX45MP platforms.
1010

11+
config SIFIVE_CCACHE
12+
bool "Sifive Composable Cache controller"
13+
depends on ARCH_SIFIVE || ARCH_STARFIVE
14+
help
15+
Support for the composable cache controller on SiFive platforms.
16+
1117
endmenu

‎drivers/cache/Makefile‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
11
# SPDX-License-Identifier: GPL-2.0
22

3-
obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o
3+
obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o
4+
obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o

drivers/soc/sifive/sifive_ccache.c renamed to drivers/cache/sifive_ccache.c

Lines changed: 60 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,13 +8,16 @@
88

99
#define pr_fmt(fmt) "CCACHE: " fmt
1010

11+
#include <linux/align.h>
1112
#include <linux/debugfs.h>
1213
#include <linux/interrupt.h>
1314
#include <linux/of_irq.h>
1415
#include <linux/of_address.h>
1516
#include <linux/device.h>
1617
#include <linux/bitfield.h>
18+
#include <asm/cacheflush.h>
1719
#include <asm/cacheinfo.h>
20+
#include <asm/dma-noncoherent.h>
1821
#include <soc/sifive/sifive_ccache.h>
1922

2023
#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
@@ -39,10 +42,14 @@
3942
#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16)
4043
#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24)
4144

45+
#define SIFIVE_CCACHE_FLUSH64 0x200
46+
#define SIFIVE_CCACHE_FLUSH32 0x240
47+
4248
#define SIFIVE_CCACHE_WAYENABLE 0x08
4349
#define SIFIVE_CCACHE_ECCINJECTERR 0x40
4450

4551
#define SIFIVE_CCACHE_MAX_ECCINTR 4
52+
#define SIFIVE_CCACHE_LINE_SIZE 64
4653

4754
static void __iomem *ccache_base;
4855
static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
@@ -56,6 +63,11 @@ enum {
5663
DIR_UNCORR,
5764
};
5865

66+
enum {
67+
QUIRK_NONSTANDARD_CACHE_OPS = BIT(0),
68+
QUIRK_BROKEN_DATA_UNCORR = BIT(1),
69+
};
70+
5971
#ifdef CONFIG_DEBUG_FS
6072
static struct dentry *sifive_test;
6173

@@ -106,6 +118,8 @@ static void ccache_config_read(void)
106118
static const struct of_device_id sifive_ccache_ids[] = {
107119
{ .compatible = "sifive,fu540-c000-ccache" },
108120
{ .compatible = "sifive,fu740-c000-ccache" },
121+
{ .compatible = "starfive,jh7100-ccache",
122+
.data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS | QUIRK_BROKEN_DATA_UNCORR) },
109123
{ .compatible = "sifive,ccache0" },
110124
{ /* end of table */ }
111125
};
@@ -124,6 +138,34 @@ int unregister_sifive_ccache_error_notifier(struct notifier_block *nb)
124138
}
125139
EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier);
126140

141+
#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
142+
static void ccache_flush_range(phys_addr_t start, size_t len)
143+
{
144+
phys_addr_t end = start + len;
145+
phys_addr_t line;
146+
147+
if (!len)
148+
return;
149+
150+
mb();
151+
for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end;
152+
line += SIFIVE_CCACHE_LINE_SIZE) {
153+
#ifdef CONFIG_32BIT
154+
writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32);
155+
#else
156+
writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64);
157+
#endif
158+
mb();
159+
}
160+
}
161+
162+
static const struct riscv_nonstd_cache_ops ccache_mgmt_ops __initconst = {
163+
.wback = &ccache_flush_range,
164+
.inv = &ccache_flush_range,
165+
.wback_inv = &ccache_flush_range,
166+
};
167+
#endif /* CONFIG_RISCV_NONSTANDARD_CACHE_OPS */
168+
127169
static int ccache_largest_wayenabled(void)
128170
{
129171
return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF;
@@ -210,11 +252,15 @@ static int __init sifive_ccache_init(void)
210252
struct device_node *np;
211253
struct resource res;
212254
int i, rc, intr_num;
255+
const struct of_device_id *match;
256+
unsigned long quirks;
213257

214-
np = of_find_matching_node(NULL, sifive_ccache_ids);
258+
np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match);
215259
if (!np)
216260
return -ENODEV;
217261

262+
quirks = (uintptr_t)match->data;
263+
218264
if (of_address_to_resource(np, 0, &res)) {
219265
rc = -ENODEV;
220266
goto err_node_put;
@@ -240,6 +286,10 @@ static int __init sifive_ccache_init(void)
240286

241287
for (i = 0; i < intr_num; i++) {
242288
g_irq[i] = irq_of_parse_and_map(np, i);
289+
290+
if (i == DATA_UNCORR && (quirks & QUIRK_BROKEN_DATA_UNCORR))
291+
continue;
292+
243293
rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc",
244294
NULL);
245295
if (rc) {
@@ -249,6 +299,14 @@ static int __init sifive_ccache_init(void)
249299
}
250300
of_node_put(np);
251301

302+
#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
303+
if (quirks & QUIRK_NONSTANDARD_CACHE_OPS) {
304+
riscv_cbom_block_size = SIFIVE_CCACHE_LINE_SIZE;
305+
riscv_noncoherent_supported();
306+
riscv_noncoherent_register_cache_ops(&ccache_mgmt_ops);
307+
}
308+
#endif
309+
252310
ccache_config_read();
253311

254312
ccache_cache_ops.get_priv_group = ccache_get_priv_group;
@@ -269,4 +327,4 @@ static int __init sifive_ccache_init(void)
269327
return rc;
270328
}
271329

272-
device_initcall(sifive_ccache_init);
330+
arch_initcall(sifive_ccache_init);

‎drivers/soc/Kconfig‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,6 @@ source "drivers/soc/qcom/Kconfig"
2222
source "drivers/soc/renesas/Kconfig"
2323
source "drivers/soc/rockchip/Kconfig"
2424
source "drivers/soc/samsung/Kconfig"
25-
source "drivers/soc/sifive/Kconfig"
2625
source "drivers/soc/sunxi/Kconfig"
2726
source "drivers/soc/tegra/Kconfig"
2827
source "drivers/soc/ti/Kconfig"

‎drivers/soc/Makefile‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,6 @@ obj-y += qcom/
2828
obj-y += renesas/
2929
obj-y += rockchip/
3030
obj-$(CONFIG_SOC_SAMSUNG) += samsung/
31-
obj-y += sifive/
3231
obj-y += sunxi/
3332
obj-$(CONFIG_ARCH_TEGRA) += tegra/
3433
obj-y += ti/

‎drivers/soc/sifive/Kconfig‎

Lines changed: 0 additions & 10 deletions
This file was deleted.

‎drivers/soc/sifive/Makefile‎

Lines changed: 0 additions & 3 deletions
This file was deleted.

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