@@ -94,8 +94,6 @@ static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev,
9494 case AMDGPU_RING_TYPE_VCN_ENC :
9595 case AMDGPU_RING_TYPE_VCN_JPEG :
9696 ip_blk = AMDGPU_XCP_VCN ;
97- if (aqua_vanjaram_xcp_vcn_shared (adev ))
98- inst_mask = 1 << (inst_idx * 2 );
9997 break ;
10098 default :
10199 DRM_ERROR ("Not support ring type %d!" , ring -> funcs -> type );
@@ -105,6 +103,8 @@ static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev,
105103 for (xcp_id = 0 ; xcp_id < adev -> xcp_mgr -> num_xcps ; xcp_id ++ ) {
106104 if (adev -> xcp_mgr -> xcp [xcp_id ].ip [ip_blk ].inst_mask & inst_mask ) {
107105 ring -> xcp_id = xcp_id ;
106+ dev_dbg (adev -> dev , "ring:%s xcp_id :%u" , ring -> name ,
107+ ring -> xcp_id );
108108 if (ring -> funcs -> type == AMDGPU_RING_TYPE_COMPUTE )
109109 adev -> gfx .enforce_isolation [xcp_id ].xcp_id = xcp_id ;
110110 break ;
@@ -394,38 +394,31 @@ static int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int x
394394 struct amdgpu_xcp_ip * ip )
395395{
396396 struct amdgpu_device * adev = xcp_mgr -> adev ;
397+ int num_sdma , num_vcn , num_shared_vcn , num_xcp ;
397398 int num_xcc_xcp , num_sdma_xcp , num_vcn_xcp ;
398- int num_sdma , num_vcn ;
399399
400400 num_sdma = adev -> sdma .num_instances ;
401401 num_vcn = adev -> vcn .num_vcn_inst ;
402+ num_shared_vcn = 1 ;
403+
404+ num_xcc_xcp = adev -> gfx .num_xcc_per_xcp ;
405+ num_xcp = NUM_XCC (adev -> gfx .xcc_mask ) / num_xcc_xcp ;
402406
403407 switch (xcp_mgr -> mode ) {
404408 case AMDGPU_SPX_PARTITION_MODE :
405- num_sdma_xcp = num_sdma ;
406- num_vcn_xcp = num_vcn ;
407- break ;
408409 case AMDGPU_DPX_PARTITION_MODE :
409- num_sdma_xcp = num_sdma / 2 ;
410- num_vcn_xcp = num_vcn / 2 ;
411- break ;
412410 case AMDGPU_TPX_PARTITION_MODE :
413- num_sdma_xcp = num_sdma / 3 ;
414- num_vcn_xcp = num_vcn / 3 ;
415- break ;
416411 case AMDGPU_QPX_PARTITION_MODE :
417- num_sdma_xcp = num_sdma / 4 ;
418- num_vcn_xcp = num_vcn / 4 ;
419- break ;
420412 case AMDGPU_CPX_PARTITION_MODE :
421- num_sdma_xcp = 2 ;
422- num_vcn_xcp = num_vcn ? 1 : 0 ;
413+ num_sdma_xcp = DIV_ROUND_UP ( num_sdma , num_xcp ) ;
414+ num_vcn_xcp = DIV_ROUND_UP ( num_vcn , num_xcp ) ;
423415 break ;
424416 default :
425417 return - EINVAL ;
426418 }
427419
428- num_xcc_xcp = adev -> gfx .num_xcc_per_xcp ;
420+ if (num_vcn && num_xcp > num_vcn )
421+ num_shared_vcn = num_xcp / num_vcn ;
429422
430423 switch (ip_id ) {
431424 case AMDGPU_XCP_GFXHUB :
@@ -441,7 +434,8 @@ static int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int x
441434 ip -> ip_funcs = & sdma_v4_4_2_xcp_funcs ;
442435 break ;
443436 case AMDGPU_XCP_VCN :
444- ip -> inst_mask = XCP_INST_MASK (num_vcn_xcp , xcp_id );
437+ ip -> inst_mask =
438+ XCP_INST_MASK (num_vcn_xcp , xcp_id / num_shared_vcn );
445439 /* TODO : Assign IP funcs */
446440 break ;
447441 default :
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