@@ -2665,6 +2665,7 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
26652665 bool dsc ,
26662666 struct link_config_limits * limits )
26672667{
2668+ struct intel_display * display = to_intel_display (intel_dp );
26682669 bool is_mst = intel_crtc_has_type (crtc_state , INTEL_OUTPUT_DP_MST );
26692670 struct intel_connector * connector =
26702671 to_intel_connector (conn_state -> connector );
@@ -2677,8 +2678,7 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
26772678 limits -> min_lane_count = intel_dp_min_lane_count (intel_dp );
26782679 limits -> max_lane_count = intel_dp_max_lane_count (intel_dp );
26792680
2680- limits -> pipe .min_bpp = intel_dp_in_hdr_mode (conn_state ) ? 30 :
2681- intel_dp_min_bpp (crtc_state -> output_format );
2681+ limits -> pipe .min_bpp = intel_dp_min_bpp (crtc_state -> output_format );
26822682 if (is_mst ) {
26832683 /*
26842684 * FIXME: If all the streams can't fit into the link with their
@@ -2694,6 +2694,19 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
26942694 respect_downstream_limits );
26952695 }
26962696
2697+ if (!dsc && intel_dp_in_hdr_mode (conn_state )) {
2698+ if (intel_dp_supports_dsc (intel_dp , connector , crtc_state ) &&
2699+ limits -> pipe .max_bpp >= 30 )
2700+ limits -> pipe .min_bpp = max (limits -> pipe .min_bpp , 30 );
2701+ else
2702+ drm_dbg_kms (display -> drm ,
2703+ "[CONNECTOR:%d:%s] Can't force 30 bpp for HDR (pipe bpp: %d-%d DSC-support: %s)\n" ,
2704+ connector -> base .base .id , connector -> base .name ,
2705+ limits -> pipe .min_bpp , limits -> pipe .max_bpp ,
2706+ str_yes_no (intel_dp_supports_dsc (intel_dp , connector ,
2707+ crtc_state )));
2708+ }
2709+
26972710 if (dsc && !intel_dp_dsc_compute_pipe_bpp_limits (connector , limits ))
26982711 return false;
26992712
@@ -2825,10 +2838,11 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
28252838 }
28262839
28272840 drm_dbg_kms (display -> drm ,
2828- "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n" ,
2841+ "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " HDR %s link rate required %d available %d\n" ,
28292842 pipe_config -> lane_count , pipe_config -> port_clock ,
28302843 pipe_config -> pipe_bpp ,
28312844 FXP_Q4_ARGS (pipe_config -> dsc .compressed_bpp_x16 ),
2845+ str_yes_no (intel_dp_in_hdr_mode (conn_state )),
28322846 intel_dp_config_required_rate (pipe_config ),
28332847 intel_dp_max_link_data_rate (intel_dp ,
28342848 pipe_config -> port_clock ,
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