55 * Copyright (c) 2015 The Linux Foundation. All rights reserved.
66 */
77
8- #define EDL_PATCH_CMD_OPCODE ( 0xFC00)
9- #define EDL_NVM_ACCESS_OPCODE ( 0xFC0B)
10- #define EDL_WRITE_BD_ADDR_OPCODE ( 0xFC14)
11- #define EDL_PATCH_CMD_LEN (1)
12- #define EDL_PATCH_VER_REQ_CMD ( 0x19)
13- #define EDL_PATCH_TLV_REQ_CMD ( 0x1E)
14- #define EDL_GET_BUILD_INFO_CMD ( 0x20)
15- #define EDL_GET_BID_REQ_CMD ( 0x23)
16- #define EDL_NVM_ACCESS_SET_REQ_CMD ( 0x01)
17- #define EDL_PATCH_CONFIG_CMD ( 0x28)
18- #define MAX_SIZE_PER_TLV_SEGMENT ( 243)
19- #define QCA_PRE_SHUTDOWN_CMD ( 0xFC08)
20- #define QCA_DISABLE_LOGGING ( 0xFC17)
21-
22- #define EDL_CMD_REQ_RES_EVT ( 0x00)
23- #define EDL_PATCH_VER_RES_EVT ( 0x19)
24- #define EDL_APP_VER_RES_EVT ( 0x02)
25- #define EDL_TVL_DNLD_RES_EVT ( 0x04)
26- #define EDL_CMD_EXE_STATUS_EVT ( 0x00)
27- #define EDL_SET_BAUDRATE_RSP_EVT ( 0x92)
28- #define EDL_NVM_ACCESS_CODE_EVT ( 0x0B)
29- #define EDL_PATCH_CONFIG_RES_EVT ( 0x00)
30- #define QCA_DISABLE_LOGGING_SUB_OP ( 0x14)
8+ #define EDL_PATCH_CMD_OPCODE 0xFC00
9+ #define EDL_NVM_ACCESS_OPCODE 0xFC0B
10+ #define EDL_WRITE_BD_ADDR_OPCODE 0xFC14
11+ #define EDL_PATCH_CMD_LEN 1
12+ #define EDL_PATCH_VER_REQ_CMD 0x19
13+ #define EDL_PATCH_TLV_REQ_CMD 0x1E
14+ #define EDL_GET_BUILD_INFO_CMD 0x20
15+ #define EDL_GET_BID_REQ_CMD 0x23
16+ #define EDL_NVM_ACCESS_SET_REQ_CMD 0x01
17+ #define EDL_PATCH_CONFIG_CMD 0x28
18+ #define MAX_SIZE_PER_TLV_SEGMENT 243
19+ #define QCA_PRE_SHUTDOWN_CMD 0xFC08
20+ #define QCA_DISABLE_LOGGING 0xFC17
21+
22+ #define EDL_CMD_REQ_RES_EVT 0x00
23+ #define EDL_PATCH_VER_RES_EVT 0x19
24+ #define EDL_APP_VER_RES_EVT 0x02
25+ #define EDL_TVL_DNLD_RES_EVT 0x04
26+ #define EDL_CMD_EXE_STATUS_EVT 0x00
27+ #define EDL_SET_BAUDRATE_RSP_EVT 0x92
28+ #define EDL_NVM_ACCESS_CODE_EVT 0x0B
29+ #define EDL_PATCH_CONFIG_RES_EVT 0x00
30+ #define QCA_DISABLE_LOGGING_SUB_OP 0x14
3131
3232#define EDL_TAG_ID_BD_ADDR 2
33- #define EDL_TAG_ID_HCI (17)
34- #define EDL_TAG_ID_DEEP_SLEEP (27)
33+ #define EDL_TAG_ID_HCI 17
34+ #define EDL_TAG_ID_DEEP_SLEEP 27
3535
3636#define QCA_WCN3990_POWERON_PULSE 0xFC
3737#define QCA_WCN3990_POWEROFF_PULSE 0xC0
3838
3939#define QCA_HCI_CC_OPCODE 0xFC00
4040#define QCA_HCI_CC_SUCCESS 0x00
4141
42- #define QCA_WCN3991_SOC_ID ( 0x40014320)
42+ #define QCA_WCN3991_SOC_ID 0x40014320
4343
4444/* QCA chipset version can be decided by patch and SoC
4545 * version, combination with upper 2 bytes from SoC
4848#define get_soc_ver (soc_id , rom_ver ) \
4949 ((le32_to_cpu(soc_id) << 16) | (le16_to_cpu(rom_ver)))
5050
51- #define QCA_HSP_GF_SOC_ID 0x1200
52- #define QCA_HSP_GF_SOC_MASK 0x0000ff00
51+ #define QCA_HSP_GF_SOC_ID 0x1200
52+ #define QCA_HSP_GF_SOC_MASK 0x0000ff00
5353
5454enum qca_baudrate {
55- QCA_BAUDRATE_115200 = 0 ,
55+ QCA_BAUDRATE_115200 = 0 ,
5656 QCA_BAUDRATE_57600 ,
5757 QCA_BAUDRATE_38400 ,
5858 QCA_BAUDRATE_19200 ,
@@ -71,7 +71,7 @@ enum qca_baudrate {
7171 QCA_BAUDRATE_1600000 ,
7272 QCA_BAUDRATE_3200000 ,
7373 QCA_BAUDRATE_3500000 ,
74- QCA_BAUDRATE_AUTO = 0xFE ,
74+ QCA_BAUDRATE_AUTO = 0xFE ,
7575 QCA_BAUDRATE_RESERVED
7676};
7777
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