|
| 1 | +/* |
| 2 | + * Copyright (C) 2023 Advanced Micro Devices, Inc. |
| 3 | + * |
| 4 | + * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | + * copy of this software and associated documentation files (the "Software"), |
| 6 | + * to deal in the Software without restriction, including without limitation |
| 7 | + * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | + * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | + * Software is furnished to do so, subject to the following conditions: |
| 10 | + * |
| 11 | + * The above copyright notice and this permission notice shall be included |
| 12 | + * in all copies or substantial portions of the Software. |
| 13 | + * |
| 14 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 15 | + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
| 18 | + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 19 | + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 20 | + */ |
| 21 | +#ifndef _smuio_10_0_2_OFFSET_HEADER |
| 22 | + |
| 23 | +// addressBlock: smuio_smuio_misc_SmuSmuioDec |
| 24 | +// base address: 0x5a000 |
| 25 | +#define mmSMUIO_MCM_CONFIG 0x0023 |
| 26 | +#define mmSMUIO_MCM_CONFIG_BASE_IDX 0 |
| 27 | +#define mmIP_DISCOVERY_VERSION 0x0000 |
| 28 | +#define mmIP_DISCOVERY_VERSION_BASE_IDX 1 |
| 29 | +#define mmIO_SMUIO_PINSTRAP 0x01b1 |
| 30 | +#define mmIO_SMUIO_PINSTRAP_BASE_IDX 1 |
| 31 | +#define mmSCRATCH_REGISTER0 0x01b2 |
| 32 | +#define mmSCRATCH_REGISTER0_BASE_IDX 1 |
| 33 | +#define mmSCRATCH_REGISTER1 0x01b3 |
| 34 | +#define mmSCRATCH_REGISTER1_BASE_IDX 1 |
| 35 | +#define mmSCRATCH_REGISTER2 0x01b4 |
| 36 | +#define mmSCRATCH_REGISTER2_BASE_IDX 1 |
| 37 | +#define mmSCRATCH_REGISTER3 0x01b5 |
| 38 | +#define mmSCRATCH_REGISTER3_BASE_IDX 1 |
| 39 | +#define mmSCRATCH_REGISTER4 0x01b6 |
| 40 | +#define mmSCRATCH_REGISTER4_BASE_IDX 1 |
| 41 | +#define mmSCRATCH_REGISTER5 0x01b7 |
| 42 | +#define mmSCRATCH_REGISTER5_BASE_IDX 1 |
| 43 | +#define mmSCRATCH_REGISTER6 0x01b8 |
| 44 | +#define mmSCRATCH_REGISTER6_BASE_IDX 1 |
| 45 | +#define mmSCRATCH_REGISTER7 0x01b9 |
| 46 | +#define mmSCRATCH_REGISTER7_BASE_IDX 1 |
| 47 | + |
| 48 | + |
| 49 | +// addressBlock: smuio_smuio_reset_SmuSmuioDec |
| 50 | +// base address: 0x5a300 |
| 51 | +#define mmSMUIO_MP_RESET_INTR 0x00c1 |
| 52 | +#define mmSMUIO_MP_RESET_INTR_BASE_IDX 0 |
| 53 | +#define mmSMUIO_SOC_HALT 0x00c2 |
| 54 | +#define mmSMUIO_SOC_HALT_BASE_IDX 0 |
| 55 | +#define mmSMUIO_GFX_MISC_CNTL 0x00c8 |
| 56 | +#define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0 |
| 57 | + |
| 58 | + |
| 59 | +// addressBlock: smuio_smuio_ccxctrl_SmuSmuioDec |
| 60 | +// base address: 0x5a000 |
| 61 | +#define mmPWROK_REFCLK_GAP_CYCLES 0x0001 |
| 62 | +#define mmPWROK_REFCLK_GAP_CYCLES_BASE_IDX 1 |
| 63 | +#define mmGOLDEN_TSC_INCREMENT_UPPER 0x0004 |
| 64 | +#define mmGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX 1 |
| 65 | +#define mmGOLDEN_TSC_INCREMENT_LOWER 0x0005 |
| 66 | +#define mmGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX 1 |
| 67 | +#define mmGOLDEN_TSC_COUNT_UPPER 0x0025 |
| 68 | +#define mmGOLDEN_TSC_COUNT_UPPER_BASE_IDX 1 |
| 69 | +#define mmGOLDEN_TSC_COUNT_LOWER 0x0026 |
| 70 | +#define mmGOLDEN_TSC_COUNT_LOWER_BASE_IDX 1 |
| 71 | +#define mmGFX_GOLDEN_TSC_SHADOW_UPPER 0x0029 |
| 72 | +#define mmGFX_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1 |
| 73 | +#define mmGFX_GOLDEN_TSC_SHADOW_LOWER 0x002a |
| 74 | +#define mmGFX_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1 |
| 75 | +#define mmSOC_GOLDEN_TSC_SHADOW_UPPER 0x002b |
| 76 | +#define mmSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1 |
| 77 | +#define mmSOC_GOLDEN_TSC_SHADOW_LOWER 0x002c |
| 78 | +#define mmSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1 |
| 79 | +#define mmSOC_GAP_PWROK 0x002d |
| 80 | +#define mmSOC_GAP_PWROK_BASE_IDX 1 |
| 81 | + |
| 82 | +// addressBlock: smuio_smuio_swtimer_SmuSmuioDec |
| 83 | +// base address: 0x5ac40 |
| 84 | +#define mmPWR_VIRT_RESET_REQ 0x0110 |
| 85 | +#define mmPWR_VIRT_RESET_REQ_BASE_IDX 1 |
| 86 | +#define mmPWR_DISP_TIMER_CONTROL 0x0111 |
| 87 | +#define mmPWR_DISP_TIMER_CONTROL_BASE_IDX 1 |
| 88 | +#define mmPWR_DISP_TIMER2_CONTROL 0x0113 |
| 89 | +#define mmPWR_DISP_TIMER2_CONTROL_BASE_IDX 1 |
| 90 | +#define mmPWR_DISP_TIMER_GLOBAL_CONTROL 0x0115 |
| 91 | +#define mmPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX 1 |
| 92 | +#define mmPWR_IH_CONTROL 0x0116 |
| 93 | +#define mmPWR_IH_CONTROL_BASE_IDX 1 |
| 94 | + |
| 95 | +// addressBlock: smuio_smuio_svi0_SmuSmuioDec |
| 96 | +// base address: 0x6f000 |
| 97 | +#define mmSMUSVI0_TEL_PLANE0 0x520e |
| 98 | +#define mmSMUSVI0_TEL_PLANE0_BASE_IDX 1 |
| 99 | +#define mmSMUSVI0_PLANE0_CURRENTVID 0x5217 |
| 100 | +#define mmSMUSVI0_PLANE0_CURRENTVID_BASE_IDX 1 |
| 101 | + |
| 102 | +#endif |
0 commit comments