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perf vendor events amd: Add Zen 5 core events
Add core events taken from Section 1.4 "Core Performance Monitor Counters" of the Performance Monitor Counters for AMD Family 1Ah Model 00h-0Fh Processors document available at the link below. This constitutes events which capture information on op dispatch, execution and retirement, branch prediction, L1 and L2 cache activity, TLB activity, etc. Reviewed-by: Ian Rogers <irogers@google.com> Signed-off-by: Sandipan Das <sandipan.das@amd.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ananth Narayan <ananth.narayan@amd.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Stephane Eranian <eranian@google.com> Link: https://bugzilla.kernel.org/attachment.cgi?id=305974 Link: https://lore.kernel.org/r/668d194241bf0d42dc37f1c5af8131069a0bd82c.1714717230.git.sandipan.das@amd.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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‎tools/perf/pmu-events/arch/x86/amdzen5/branch-prediction.json‎

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[
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_hit",
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"EventCode": "0x84",
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"BriefDescription": "Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
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},
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k",
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"EventCode": "0x85",
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"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages.",
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"UMask": "0x01"
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},
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m",
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"EventCode": "0x85",
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"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages.",
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"UMask": "0x02"
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},
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g",
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"EventCode": "0x85",
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"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages.",
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"UMask": "0x04"
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},
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k",
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"EventCode": "0x85",
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"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
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"UMask": "0x08"
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},
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_miss.all",
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"EventCode": "0x85",
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"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes.",
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"UMask": "0x0f"
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},
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{
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"EventName": "bp_l2_btb_correct",
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"EventCode": "0x8b",
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"BriefDescription": "L2 branch prediction overrides existing prediction (speculative)."
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},
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{
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"EventName": "bp_dyn_ind_pred",
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"EventCode": "0x8e",
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"BriefDescription": "Dynamic indirect predictions (branch used the indirect predictor to make a prediction)."
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},
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{
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"EventName": "bp_de_redirect",
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"EventCode": "0x91",
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"BriefDescription": "Number of times an early redirect is sent to branch predictor. This happens when either the decoder or dispatch logic is able to detect that the branch predictor needs to be redirected."
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},
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{
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"EventName": "bp_l1_tlb_fetch_hit.if4k",
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"EventCode": "0x94",
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"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
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"UMask": "0x01"
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},
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{
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"EventName": "bp_l1_tlb_fetch_hit.if2m",
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"EventCode": "0x94",
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"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 2M pages.",
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"UMask": "0x02"
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},
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{
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"EventName": "bp_l1_tlb_fetch_hit.if1g",
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"EventCode": "0x94",
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"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 1G pages.",
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"UMask": "0x04"
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},
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{
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"EventName": "bp_l1_tlb_fetch_hit.all",
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"EventCode": "0x94",
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"BriefDescription": "Instruction fetches that hit in the L1 ITLB for all page sizes.",
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"UMask": "0x07"
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},
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{
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"EventName": "bp_redirects.resync",
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"EventCode": "0x9f",
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"BriefDescription": "Redirects of the branch predictor caused by resyncs.",
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"UMask": "0x01"
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},
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{
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"EventName": "bp_redirects.ex_redir",
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"EventCode": "0x9f",
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"BriefDescription": "Redirects of the branch predictor caused by mispredicts.",
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"UMask": "0x02"
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},
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{
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"EventName": "bp_redirects.all",
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"EventCode": "0x9f",
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"BriefDescription": "Redirects of the branch predictor."
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}
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]

‎tools/perf/pmu-events/arch/x86/amdzen5/decode.json‎

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[
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{
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"EventName": "de_op_queue_empty",
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"EventCode": "0xa9",
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"BriefDescription": "Cycles where the op queue is empty. Such cycles indicate that the front-end is not delivering instructions fast enough."
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},
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{
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"EventName": "de_src_op_disp.x86_decoder",
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"EventCode": "0xaa",
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"BriefDescription": "Ops dispatched from x86 decoder.",
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"UMask": "0x01"
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},
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{
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"EventName": "de_src_op_disp.op_cache",
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"EventCode": "0xaa",
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"BriefDescription": "Ops dispatched from op cache.",
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"UMask": "0x02"
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},
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{
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"EventName": "de_src_op_disp.all",
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"EventCode": "0xaa",
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"BriefDescription": "Ops dispatched from any source.",
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"UMask": "0x07"
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},
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{
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"EventName": "de_dis_ops_from_decoder.any_fp_dispatch",
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"EventCode": "0xab",
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"BriefDescription": "Number of ops dispatched to the floating-point unit.",
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"UMask": "0x04"
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},
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{
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"EventName": "de_dis_ops_from_decoder.any_integer_dispatch",
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"EventCode": "0xab",
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"BriefDescription": "Number of ops dispatched to the integer execution unit.",
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"UMask": "0x08"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.int_phy_reg_file_rsrc_stall",
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"EventCode": "0xae",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to an integer physical register file resource stall.",
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"UMask": "0x01"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.load_queue_rsrc_stall",
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"EventCode": "0xae",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a lack of load queue tokens.",
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"UMask": "0x02"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.store_queue_rsrc_stall",
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"EventCode": "0xae",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a lack of store queue tokens.",
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"UMask": "0x04"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.taken_brnch_buffer_rsrc",
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"EventCode": "0xae",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a taken branch buffer resource stall.",
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"UMask": "0x10"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part1.fp_sch_rsrc_stall",
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"EventCode": "0xae",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a floating-point non-schedulable queue token stall.",
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"UMask": "0x40"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.al_tokens",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of ALU tokens.",
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"UMask": "0x01"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.ag_tokens",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of agen tokens.",
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"UMask": "0x02"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.ex_flush_recovery",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a pending integer execution flush recovery.",
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"UMask": "0x04"
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},
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{
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"EventName": "de_dispatch_stall_cycle_dynamic_tokens_part2.retq",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to unavailability of retire queue tokens.",
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"UMask": "0x20"
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},
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{
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"EventName": "de_no_dispatch_per_slot.no_ops_from_frontend",
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"EventCode": "0x1a0",
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"BriefDescription": "In each cycle counts dispatch slots left empty because the front-end did not supply ops.",
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"UMask": "0x01"
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},
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{
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"EventName": "de_no_dispatch_per_slot.backend_stalls",
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"EventCode": "0x1a0",
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"BriefDescription": "In each cycle counts ops unable to dispatch because of back-end stalls.",
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"UMask": "0x1e"
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},
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{
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"EventName": "de_no_dispatch_per_slot.smt_contention",
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"EventCode": "0x1a0",
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"BriefDescription": "In each cycle counts ops unable to dispatch because the dispatch cycle was granted to the other SMT thread.",
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"UMask": "0x60"
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},
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{
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"EventName": "de_additional_resource_stalls.dispatch_stalls",
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"EventCode": "0x1a2",
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"BriefDescription": "Counts additional cycles where dispatch is stalled due to a lack of dispatch resources.",
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"UMask": "0x30"
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}
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]

‎tools/perf/pmu-events/arch/x86/amdzen5/execution.json‎

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[
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{
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"EventName": "ex_ret_instr",
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"EventCode": "0xc0",
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"BriefDescription": "Retired instructions."
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},
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{
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"EventName": "ex_ret_ops",
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"EventCode": "0xc1",
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"BriefDescription": "Retired macro-ops."
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},
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{
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"EventName": "ex_ret_brn",
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"EventCode": "0xc2",
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"BriefDescription": "Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
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},
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{
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"EventName": "ex_ret_brn_misp",
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"EventCode": "0xc3",
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"BriefDescription": "Retired branch instructions mispredicted."
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},
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{
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"EventName": "ex_ret_brn_tkn",
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"EventCode": "0xc4",
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"BriefDescription": "Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
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},
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{
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"EventName": "ex_ret_brn_tkn_misp",
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"EventCode": "0xc5",
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"BriefDescription": "Retired taken branch instructions mispredicted."
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},
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{
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"EventName": "ex_ret_brn_far",
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"EventCode": "0xc6",
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"BriefDescription": "Retired far control transfers (far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction."
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},
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{
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"EventName": "ex_ret_near_ret",
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"EventCode": "0xc8",
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"BriefDescription": "Retired near returns (RET or RET Iw)."
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},
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{
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"EventName": "ex_ret_near_ret_mispred",
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"EventCode": "0xc9",
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"BriefDescription": "Retired near returns mispredicted. Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."
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},
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{
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"EventName": "ex_ret_brn_ind_misp",
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"EventCode": "0xca",
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"BriefDescription": "Retired indirect branch instructions mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."
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},
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{
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"EventName": "ex_ret_mmx_fp_instr.x87",
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"EventCode": "0xcb",
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"BriefDescription": "Retired x87 instructions.",
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"UMask": "0x01"
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},
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{
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"EventName": "ex_ret_mmx_fp_instr.mmx",
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"EventCode": "0xcb",
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"BriefDescription": "Retired MMX instructions.",
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"UMask": "0x02"
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},
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{
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"EventName": "ex_ret_mmx_fp_instr.sse",
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"EventCode": "0xcb",
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"BriefDescription": "Retired SSE instructions (includes SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42 and AVX).",
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"UMask": "0x04"
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},
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{
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"EventName": "ex_ret_ind_brch_instr",
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"EventCode": "0xcc",
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"BriefDescription": "Retired indirect branch instructions."
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},
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{
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"EventName": "ex_ret_cond",
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"EventCode": "0xd1",
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"BriefDescription": "Retired conditional branch instructions."
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},
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{
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"EventName": "ex_div_busy",
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"EventCode": "0xd3",
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"BriefDescription": "Number of cycles the divider is busy."
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},
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{
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"EventName": "ex_div_count",
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"EventCode": "0xd4",
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"BriefDescription": "Divide ops executed."
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},
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{
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"EventName": "ex_no_retire.empty",
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"EventCode": "0xd6",
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"BriefDescription": "Cycles with no retire due to the lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects).",
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"UMask": "0x01"
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},
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{
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"EventName": "ex_no_retire.not_complete",
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"EventCode": "0xd6",
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"BriefDescription": "Cycles with no retire while the oldest op is waiting to be executed.",
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"UMask": "0x02"
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},
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{
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"EventName": "ex_no_retire.other",
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"EventCode": "0xd6",
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"BriefDescription": "Cycles with no retire caused by other reasons (retire breaks, traps, faults, etc.).",
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"UMask": "0x08"
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},
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{
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"EventName": "ex_no_retire.thread_not_selected",
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"EventCode": "0xd6",
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"BriefDescription": "Cycles with no retire because thread arbitration did not select the thread.",
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"UMask": "0x10"
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},
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{
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"EventName": "ex_no_retire.load_not_complete",
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"EventCode": "0xd6",
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"BriefDescription": "Cycles with no retire while the oldest op is waiting for load data.",
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"UMask": "0xa2"
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},
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{
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"EventName": "ex_no_retire.all",
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"EventCode": "0xd6",
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"BriefDescription": "Cycles with no retire for any reason.",
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"UMask": "0x1b"
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},
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{
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"EventName": "ex_ret_ucode_instr",
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"EventCode": "0x1c1",
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"BriefDescription": "Retired microcoded instructions."
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},
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{
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"EventName": "ex_ret_ucode_ops",
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"EventCode": "0x1c2",
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"BriefDescription": "Retired microcode ops."
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},
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{
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"EventName": "ex_ret_msprd_brnch_instr_dir_msmtch",
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"EventCode": "0x1c7",
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"BriefDescription": "Retired branch instructions mispredicted due to direction mismatch."
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},
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{
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"EventName": "ex_ret_uncond_brnch_instr_mispred",
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"EventCode": "0x1c8",
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"BriefDescription": "Retired unconditional indirect branch instructions mispredicted."
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},
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{
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"EventName": "ex_ret_uncond_brnch_instr",
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"EventCode": "0x1c9",
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"BriefDescription": "Retired unconditional branch instructions."
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},
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{
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"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
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"EventCode": "0x1cf",
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"BriefDescription": "Ops tagged by IBS.",
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"UMask": "0x01"
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},
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{
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"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
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"EventCode": "0x1cf",
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"BriefDescription": "Ops tagged by IBS that retired.",
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"UMask": "0x02"
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},
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{
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"EventName": "ex_tagged_ibs_ops.ibs_count_rollover",
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"EventCode": "0x1cf",
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"BriefDescription": "Ops not tagged by IBS due to a previous tagged op that has not yet signaled interrupt.",
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"UMask": "0x04"
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},
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{
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"EventName": "ex_ret_fused_instr",
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"EventCode": "0x1d0",
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"BriefDescription": "Retired fused instructions."
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}
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]

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