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thermal/drivers/rockchip: Support RK3588 SoC in the thermal driver
The RK3588 SoC has seven temperature sensor ADC channels: - Chip Center - CPU Cluster 1 (Dual A76 "Big" Cores) - CPU Cluster 2 (Dual A76 "Big" Cores) - CPU Cluster 0 (Quad A55 "Little" Cores) - Power Domain Center - Graphics Processing Unit - Neural Processing Unit Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> [rebase, squash fixes] Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20230308112253.15659-7-sebastian.reichel@collabora.com
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‎drivers/thermal/rockchip_thermal.c‎

Lines changed: 177 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -165,29 +165,49 @@ struct rockchip_thermal_data {
165165
#define TSADCV2_AUTO_CON 0x04
166166
#define TSADCV2_INT_EN 0x08
167167
#define TSADCV2_INT_PD 0x0c
168+
#define TSADCV3_AUTO_SRC_CON 0x0c
169+
#define TSADCV3_HT_INT_EN 0x14
170+
#define TSADCV3_HSHUT_GPIO_INT_EN 0x18
171+
#define TSADCV3_HSHUT_CRU_INT_EN 0x1c
172+
#define TSADCV3_INT_PD 0x24
173+
#define TSADCV3_HSHUT_PD 0x28
168174
#define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
169175
#define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
170176
#define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
177+
#define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04)
178+
#define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04)
179+
#define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04)
171180
#define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
172181
#define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
182+
#define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c
183+
#define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150
173184
#define TSADCV2_AUTO_PERIOD 0x68
174185
#define TSADCV2_AUTO_PERIOD_HT 0x6c
186+
#define TSADCV3_AUTO_PERIOD 0x154
187+
#define TSADCV3_AUTO_PERIOD_HT 0x158
175188

176189
#define TSADCV2_AUTO_EN BIT(0)
190+
#define TSADCV2_AUTO_EN_MASK BIT(16)
177191
#define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
192+
#define TSADCV3_AUTO_SRC_EN(chn) BIT(chn)
193+
#define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + chn)
178194
#define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
195+
#define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
179196

180197
#define TSADCV3_AUTO_Q_SEL_EN BIT(1)
181198

182199
#define TSADCV2_INT_SRC_EN(chn) BIT(chn)
200+
#define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
183201
#define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
184202
#define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
185203

186204
#define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
187205
#define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
206+
#define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff
188207

189208
#define TSADCV2_DATA_MASK 0xfff
190209
#define TSADCV3_DATA_MASK 0x3ff
210+
#define TSADCV4_DATA_MASK 0x1ff
191211

192212
#define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
193213
#define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
@@ -198,6 +218,8 @@ struct rockchip_thermal_data {
198218

199219
#define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */
200220
#define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
221+
#define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */
222+
#define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
201223

202224
#define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
203225
#define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
@@ -214,6 +236,12 @@ struct rockchip_thermal_data {
214236
#define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2)
215237
#define RK3568_GRF_TSADC_TSEN (0x10001 << 8)
216238

239+
#define RK3588_GRF0_TSADC_CON 0x0100
240+
241+
#define RK3588_GRF0_TSADC_TRM (0xff0077 << 0)
242+
#define RK3588_GRF0_TSADC_SHUT_2CRU (0x30003 << 10)
243+
#define RK3588_GRF0_TSADC_SHUT_2GPIO (0x70007 << 12)
244+
217245
#define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
218246
#define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
219247
#define GRF_TSADC_VCM_EN_L (0x10001 << 7)
@@ -508,6 +536,15 @@ static const struct tsadc_table rk3568_code_table[] = {
508536
{TSADCV2_DATA_MASK, 125000},
509537
};
510538

539+
static const struct tsadc_table rk3588_code_table[] = {
540+
{0, -40000},
541+
{215, -40000},
542+
{285, 25000},
543+
{350, 85000},
544+
{395, 125000},
545+
{TSADCV4_DATA_MASK, 125000},
546+
};
547+
511548
static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
512549
int temp)
513550
{
@@ -778,6 +815,25 @@ static void rk_tsadcv7_initialize(struct regmap *grf, void __iomem *regs,
778815
}
779816
}
780817

818+
static void rk_tsadcv8_initialize(struct regmap *grf, void __iomem *regs,
819+
enum tshut_polarity tshut_polarity)
820+
{
821+
writel_relaxed(TSADCV6_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
822+
writel_relaxed(TSADCV6_AUTO_PERIOD_HT_TIME,
823+
regs + TSADCV3_AUTO_PERIOD_HT);
824+
writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
825+
regs + TSADCV3_HIGHT_INT_DEBOUNCE);
826+
writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
827+
regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
828+
if (tshut_polarity == TSHUT_HIGH_ACTIVE)
829+
writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
830+
TSADCV2_AUTO_TSHUT_POLARITY_MASK,
831+
regs + TSADCV2_AUTO_CON);
832+
else
833+
writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
834+
regs + TSADCV2_AUTO_CON);
835+
}
836+
781837
static void rk_tsadcv2_irq_ack(void __iomem *regs)
782838
{
783839
u32 val;
@@ -794,6 +850,17 @@ static void rk_tsadcv3_irq_ack(void __iomem *regs)
794850
writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
795851
}
796852

853+
static void rk_tsadcv4_irq_ack(void __iomem *regs)
854+
{
855+
u32 val;
856+
857+
val = readl_relaxed(regs + TSADCV3_INT_PD);
858+
writel_relaxed(val & TSADCV4_INT_PD_CLEAR_MASK, regs + TSADCV3_INT_PD);
859+
val = readl_relaxed(regs + TSADCV3_HSHUT_PD);
860+
writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK,
861+
regs + TSADCV3_HSHUT_PD);
862+
}
863+
797864
static void rk_tsadcv2_control(void __iomem *regs, bool enable)
798865
{
799866
u32 val;
@@ -829,6 +896,18 @@ static void rk_tsadcv3_control(void __iomem *regs, bool enable)
829896
writel_relaxed(val, regs + TSADCV2_AUTO_CON);
830897
}
831898

899+
static void rk_tsadcv4_control(void __iomem *regs, bool enable)
900+
{
901+
u32 val;
902+
903+
if (enable)
904+
val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK;
905+
else
906+
val = TSADCV2_AUTO_EN_MASK;
907+
908+
writel_relaxed(val, regs + TSADCV2_AUTO_CON);
909+
}
910+
832911
static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
833912
int chn, void __iomem *regs, int *temp)
834913
{
@@ -839,6 +918,16 @@ static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
839918
return rk_tsadcv2_code_to_temp(table, val, temp);
840919
}
841920

921+
static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table,
922+
int chn, void __iomem *regs, int *temp)
923+
{
924+
u32 val;
925+
926+
val = readl_relaxed(regs + TSADCV3_DATA(chn));
927+
928+
return rk_tsadcv2_code_to_temp(table, val, temp);
929+
}
930+
842931
static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
843932
int chn, void __iomem *regs, int temp)
844933
{
@@ -873,6 +962,33 @@ static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
873962
return 0;
874963
}
875964

965+
static int rk_tsadcv3_alarm_temp(const struct chip_tsadc_table *table,
966+
int chn, void __iomem *regs, int temp)
967+
{
968+
u32 alarm_value;
969+
970+
/*
971+
* In some cases, some sensors didn't need the trip points, the
972+
* set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
973+
* in the end, ignore this case and disable the high temperature
974+
* interrupt.
975+
*/
976+
if (temp == INT_MAX) {
977+
writel_relaxed(TSADCV2_INT_SRC_EN_MASK(chn),
978+
regs + TSADCV3_HT_INT_EN);
979+
return 0;
980+
}
981+
/* Make sure the value is valid */
982+
alarm_value = rk_tsadcv2_temp_to_code(table, temp);
983+
if (alarm_value == table->data_mask)
984+
return -ERANGE;
985+
writel_relaxed(alarm_value & table->data_mask,
986+
regs + TSADCV3_COMP_INT(chn));
987+
writel_relaxed(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn),
988+
regs + TSADCV3_HT_INT_EN);
989+
return 0;
990+
}
991+
876992
static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
877993
int chn, void __iomem *regs, int temp)
878994
{
@@ -892,6 +1008,25 @@ static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
8921008
return 0;
8931009
}
8941010

1011+
static int rk_tsadcv3_tshut_temp(const struct chip_tsadc_table *table,
1012+
int chn, void __iomem *regs, int temp)
1013+
{
1014+
u32 tshut_value;
1015+
1016+
/* Make sure the value is valid */
1017+
tshut_value = rk_tsadcv2_temp_to_code(table, temp);
1018+
if (tshut_value == table->data_mask)
1019+
return -ERANGE;
1020+
1021+
writel_relaxed(tshut_value, regs + TSADCV3_COMP_SHUT(chn));
1022+
1023+
/* TSHUT will be valid */
1024+
writel_relaxed(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn),
1025+
regs + TSADCV3_AUTO_SRC_CON);
1026+
1027+
return 0;
1028+
}
1029+
8951030
static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
8961031
enum tshut_mode mode)
8971032
{
@@ -909,6 +1044,22 @@ static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
9091044
writel_relaxed(val, regs + TSADCV2_INT_EN);
9101045
}
9111046

1047+
static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs,
1048+
enum tshut_mode mode)
1049+
{
1050+
u32 val_gpio, val_cru;
1051+
1052+
if (mode == TSHUT_MODE_GPIO) {
1053+
val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
1054+
val_cru = TSADCV2_INT_SRC_EN_MASK(chn);
1055+
} else {
1056+
val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
1057+
val_gpio = TSADCV2_INT_SRC_EN_MASK(chn);
1058+
}
1059+
writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN);
1060+
writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN);
1061+
}
1062+
9121063
static const struct rockchip_tsadc_chip px30_tsadc_data = {
9131064
/* cpu, gpu */
9141065
.chn_offset = 0,
@@ -1132,6 +1283,28 @@ static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
11321283
},
11331284
};
11341285

1286+
static const struct rockchip_tsadc_chip rk3588_tsadc_data = {
1287+
/* top, big_core0, big_core1, little_core, center, gpu, npu */
1288+
.chn_offset = 0,
1289+
.chn_num = 7, /* seven channels for tsadc */
1290+
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1291+
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1292+
.tshut_temp = 95000,
1293+
.initialize = rk_tsadcv8_initialize,
1294+
.irq_ack = rk_tsadcv4_irq_ack,
1295+
.control = rk_tsadcv4_control,
1296+
.get_temp = rk_tsadcv4_get_temp,
1297+
.set_alarm_temp = rk_tsadcv3_alarm_temp,
1298+
.set_tshut_temp = rk_tsadcv3_tshut_temp,
1299+
.set_tshut_mode = rk_tsadcv3_tshut_mode,
1300+
.table = {
1301+
.id = rk3588_code_table,
1302+
.length = ARRAY_SIZE(rk3588_code_table),
1303+
.data_mask = TSADCV4_DATA_MASK,
1304+
.mode = ADC_INCREMENT,
1305+
},
1306+
};
1307+
11351308
static const struct of_device_id of_rockchip_thermal_match[] = {
11361309
{ .compatible = "rockchip,px30-tsadc",
11371310
.data = (void *)&px30_tsadc_data,
@@ -1168,6 +1341,10 @@ static const struct of_device_id of_rockchip_thermal_match[] = {
11681341
.compatible = "rockchip,rk3568-tsadc",
11691342
.data = (void *)&rk3568_tsadc_data,
11701343
},
1344+
{
1345+
.compatible = "rockchip,rk3588-tsadc",
1346+
.data = (void *)&rk3588_tsadc_data,
1347+
},
11711348
{ /* end */ },
11721349
};
11731350
MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);

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