arm64: dts: imx8mn-bsh-smm: update pinctrl to match dtschema

The dtschema requires 'grp' in the end, so update the name

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Author: MrVan

arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi

@@ -341,7 +341,7 @@
 		>;
 	};
 
-	pinctrl_pmic: pmicirq {
+	pinctrl_pmic: pmicirqgrp {
 		fsl,pins = <
 			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x040
 		>;
@@ -381,7 +381,7 @@
 		>;
 	};
 
-	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 		fsl,pins = <
 			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK			0x094
 			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD			0x0d4
@@ -392,7 +392,7 @@
 		>;
 	};
 
-	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 		fsl,pins = <
 			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK			0x096
 			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD			0x0d6

arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts

@@ -26,7 +26,7 @@
 };
 
 &iomuxc {
-	pinctrl_gpmi_nand: gpmi-nand {
+	pinctrl_gpmi_nand: gpminandgrp {
 		fsl,pins = <
 			MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE		0x00000096
 			MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B		0x00000096

arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts

@@ -136,7 +136,7 @@
 		>;
 	};
 
-	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
 		fsl,pins = <
 			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK			0x40000094
 			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD			0x0d4
@@ -152,7 +152,7 @@
 		>;
 	};
 
-	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
 		fsl,pins = <
 			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK			0x40000096
 			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD			0x0d6