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George Guochenhuacai
George Guo
authored and
chenhuacai
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LoongArch: Add detection for SC.Q support
Check the CPUCFG2_SCQ bit to determine if the current CPU supports the SC.Q instruction. Reviewed-by: Hengqi Chen <hengqi.chen@gmail.com> Tested-by: Hengqi Chen <hengqi.chen@gmail.com> Co-developed-by: Yangyang Lian <lianyangyang@kylinos.cn> Signed-off-by: Yangyang Lian <lianyangyang@kylinos.cn> Signed-off-by: George Guo <guodongtai@kylinos.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
1 parent 07d5798 commit 48543c4

5 files changed

Lines changed: 39 additions & 30 deletions

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‎arch/loongarch/include/asm/cpu-features.h‎

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@@ -35,6 +35,7 @@
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*/
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#define cpu_has_cpucfg cpu_opt(LOONGARCH_CPU_CPUCFG)
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#define cpu_has_lam cpu_opt(LOONGARCH_CPU_LAM)
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#define cpu_has_scq cpu_opt(LOONGARCH_CPU_SCQ)
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#define cpu_has_ual cpu_opt(LOONGARCH_CPU_UAL)
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#define cpu_has_fpu cpu_opt(LOONGARCH_CPU_FPU)
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#define cpu_has_lsx cpu_opt(LOONGARCH_CPU_LSX)

‎arch/loongarch/include/asm/cpu.h‎

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@@ -95,39 +95,41 @@ static inline char *id_to_core_name(unsigned int id)
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*/
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#define CPU_FEATURE_CPUCFG 0 /* CPU has CPUCFG */
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#define CPU_FEATURE_LAM 1 /* CPU has Atomic instructions */
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#define CPU_FEATURE_UAL 2 /* CPU supports unaligned access */
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#define CPU_FEATURE_FPU 3 /* CPU has FPU */
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#define CPU_FEATURE_LSX 4 /* CPU has LSX (128-bit SIMD) */
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#define CPU_FEATURE_LASX 5 /* CPU has LASX (256-bit SIMD) */
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#define CPU_FEATURE_CRC32 6 /* CPU has CRC32 instructions */
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#define CPU_FEATURE_COMPLEX 7 /* CPU has Complex instructions */
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#define CPU_FEATURE_CRYPTO 8 /* CPU has Crypto instructions */
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#define CPU_FEATURE_LVZ 9 /* CPU has Virtualization extension */
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#define CPU_FEATURE_LBT_X86 10 /* CPU has X86 Binary Translation */
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#define CPU_FEATURE_LBT_ARM 11 /* CPU has ARM Binary Translation */
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#define CPU_FEATURE_LBT_MIPS 12 /* CPU has MIPS Binary Translation */
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#define CPU_FEATURE_TLB 13 /* CPU has TLB */
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#define CPU_FEATURE_CSR 14 /* CPU has CSR */
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#define CPU_FEATURE_IOCSR 15 /* CPU has IOCSR */
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#define CPU_FEATURE_WATCH 16 /* CPU has watchpoint registers */
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#define CPU_FEATURE_VINT 17 /* CPU has vectored interrupts */
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#define CPU_FEATURE_CSRIPI 18 /* CPU has CSR-IPI */
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#define CPU_FEATURE_EXTIOI 19 /* CPU has EXT-IOI */
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#define CPU_FEATURE_PREFETCH 20 /* CPU has prefetch instructions */
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#define CPU_FEATURE_PMP 21 /* CPU has perfermance counter */
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#define CPU_FEATURE_SCALEFREQ 22 /* CPU supports cpufreq scaling */
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#define CPU_FEATURE_FLATMODE 23 /* CPU has flat mode */
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#define CPU_FEATURE_EIODECODE 24 /* CPU has EXTIOI interrupt pin decode mode */
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#define CPU_FEATURE_GUESTID 25 /* CPU has GuestID feature */
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#define CPU_FEATURE_HYPERVISOR 26 /* CPU has hypervisor (running in VM) */
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#define CPU_FEATURE_PTW 27 /* CPU has hardware page table walker */
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#define CPU_FEATURE_LSPW 28 /* CPU has LSPW (lddir/ldpte instructions) */
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#define CPU_FEATURE_MSGINT 29 /* CPU has MSG interrupt */
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#define CPU_FEATURE_AVECINT 30 /* CPU has AVEC interrupt */
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#define CPU_FEATURE_REDIRECTINT 31 /* CPU has interrupt remapping */
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#define CPU_FEATURE_SCQ 2 /* CPU has SC.Q instruction */
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#define CPU_FEATURE_UAL 3 /* CPU supports unaligned access */
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#define CPU_FEATURE_FPU 4 /* CPU has FPU */
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#define CPU_FEATURE_LSX 5 /* CPU has LSX (128-bit SIMD) */
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#define CPU_FEATURE_LASX 6 /* CPU has LASX (256-bit SIMD) */
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#define CPU_FEATURE_CRC32 7 /* CPU has CRC32 instructions */
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#define CPU_FEATURE_COMPLEX 8 /* CPU has Complex instructions */
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#define CPU_FEATURE_CRYPTO 9 /* CPU has Crypto instructions */
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#define CPU_FEATURE_LVZ 10 /* CPU has Virtualization extension */
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#define CPU_FEATURE_LBT_X86 11 /* CPU has X86 Binary Translation */
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#define CPU_FEATURE_LBT_ARM 12 /* CPU has ARM Binary Translation */
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#define CPU_FEATURE_LBT_MIPS 13 /* CPU has MIPS Binary Translation */
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#define CPU_FEATURE_TLB 14 /* CPU has TLB */
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#define CPU_FEATURE_CSR 15 /* CPU has CSR */
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#define CPU_FEATURE_IOCSR 16 /* CPU has IOCSR */
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#define CPU_FEATURE_WATCH 17 /* CPU has watchpoint registers */
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#define CPU_FEATURE_VINT 18 /* CPU has vectored interrupts */
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#define CPU_FEATURE_CSRIPI 19 /* CPU has CSR-IPI */
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#define CPU_FEATURE_EXTIOI 20 /* CPU has EXT-IOI */
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#define CPU_FEATURE_PREFETCH 21 /* CPU has prefetch instructions */
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#define CPU_FEATURE_PMP 22 /* CPU has perfermance counter */
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#define CPU_FEATURE_SCALEFREQ 23 /* CPU supports cpufreq scaling */
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#define CPU_FEATURE_FLATMODE 24 /* CPU has flat mode */
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#define CPU_FEATURE_EIODECODE 25 /* CPU has EXTIOI interrupt pin decode mode */
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#define CPU_FEATURE_GUESTID 26 /* CPU has GuestID feature */
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#define CPU_FEATURE_HYPERVISOR 27 /* CPU has hypervisor (running in VM) */
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#define CPU_FEATURE_PTW 28 /* CPU has hardware page table walker */
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#define CPU_FEATURE_LSPW 29 /* CPU has LSPW (lddir/ldpte instructions) */
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#define CPU_FEATURE_MSGINT 30 /* CPU has MSG interrupt */
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#define CPU_FEATURE_AVECINT 31 /* CPU has AVEC interrupt */
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#define CPU_FEATURE_REDIRECTINT 32 /* CPU has interrupt remapping */
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#define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG)
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#define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)
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#define LOONGARCH_CPU_SCQ BIT_ULL(CPU_FEATURE_SCQ)
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#define LOONGARCH_CPU_UAL BIT_ULL(CPU_FEATURE_UAL)
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#define LOONGARCH_CPU_FPU BIT_ULL(CPU_FEATURE_FPU)
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#define LOONGARCH_CPU_LSX BIT_ULL(CPU_FEATURE_LSX)

‎arch/loongarch/include/uapi/asm/hwcap.h‎

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@@ -18,5 +18,6 @@
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#define HWCAP_LOONGARCH_LBT_MIPS (1 << 12)
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#define HWCAP_LOONGARCH_PTW (1 << 13)
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#define HWCAP_LOONGARCH_LSPW (1 << 14)
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#define HWCAP_LOONGARCH_SCQ (1 << 15)
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#endif /* _UAPI_ASM_HWCAP_H */

‎arch/loongarch/kernel/cpu-probe.c‎

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@@ -177,6 +177,10 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
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c->options |= LOONGARCH_CPU_LAM;
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elf_hwcap |= HWCAP_LOONGARCH_LAM;
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}
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if (config & CPUCFG2_SCQ) {
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c->options |= LOONGARCH_CPU_SCQ;
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elf_hwcap |= HWCAP_LOONGARCH_SCQ;
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}
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if (config & CPUCFG2_FP) {
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c->options |= LOONGARCH_CPU_FPU;
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elf_hwcap |= HWCAP_LOONGARCH_FPU;

‎arch/loongarch/kernel/proc.c‎

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@@ -62,6 +62,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
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seq_printf(m, "Features\t\t:");
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if (cpu_has_cpucfg) seq_printf(m, " cpucfg");
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if (cpu_has_lam) seq_printf(m, " lam");
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if (cpu_has_scq) seq_printf(m, " scq");
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if (cpu_has_ual) seq_printf(m, " ual");
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if (cpu_has_fpu) seq_printf(m, " fpu");
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if (cpu_has_lsx) seq_printf(m, " lsx");

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