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Li Maalexdeucher
Li Ma
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alexdeucher
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drm/amd/swsmu: update smu v14_0_0 header files and metrics table
Update driver if, pmfw and ppsmc header files. Add new gpu_metrics_v3_0 for metrics table updated in driver if and reserve legacy metrics table to maintain backward compatibility. --- v1: Update header files and add gpu_metrics_v3_0. v2: Update smu_types.h, smu headers and drop smu_cmn_get_smc_version in smu v14_0_0. Signed-off-by: Li Ma <li.ma@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 3bba4bc commit 49c775b

6 files changed

Lines changed: 359 additions & 109 deletions

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‎drivers/gpu/drm/amd/include/kgd_pp_interface.h‎

Lines changed: 68 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1057,4 +1057,72 @@ struct gpu_metrics_v2_4 {
10571057
uint16_t average_soc_current;
10581058
uint16_t average_gfx_current;
10591059
};
1060+
1061+
struct gpu_metrics_v3_0 {
1062+
struct metrics_table_header common_header;
1063+
1064+
/* Temperature */
1065+
/* gfx temperature on APUs */
1066+
uint16_t temperature_gfx;
1067+
/* soc temperature on APUs */
1068+
uint16_t temperature_soc;
1069+
/* CPU core temperature on APUs */
1070+
uint16_t temperature_core[16];
1071+
/* skin temperature on APUs */
1072+
uint16_t temperature_skin;
1073+
1074+
/* Utilization */
1075+
/* time filtered GFX busy % [0-100] */
1076+
uint16_t average_gfx_activity;
1077+
/* time filtered VCN busy % [0-100] */
1078+
uint16_t average_vcn_activity;
1079+
/* time filtered IPU per-column busy % [0-100] */
1080+
uint16_t average_ipu_activity[8];
1081+
/* time filtered per-core C0 residency % [0-100]*/
1082+
uint16_t average_core_c0_activity[16];
1083+
/* time filtered DRAM read bandwidth [GB/sec] */
1084+
uint16_t average_dram_reads;
1085+
/* time filtered DRAM write bandwidth [GB/sec] */
1086+
uint16_t average_dram_writes;
1087+
1088+
/* Driver attached timestamp (in ns) */
1089+
uint64_t system_clock_counter;
1090+
1091+
/* Power/Energy */
1092+
/* average dGPU + APU power on A + A platform */
1093+
uint32_t average_socket_power;
1094+
/* average IPU power [W] */
1095+
uint16_t average_ipu_power;
1096+
/* average APU power [W] */
1097+
uint32_t average_apu_power;
1098+
/* average dGPU power [W] */
1099+
uint32_t average_dgpu_power;
1100+
/* sum of core power across all cores in the socket [W] */
1101+
uint32_t average_core_power;
1102+
/* calculated core power [W] */
1103+
uint16_t core_power[16];
1104+
/* maximum IRM defined STAPM power limit [W] */
1105+
uint16_t stapm_power_limit;
1106+
/* time filtered STAPM power limit [W] */
1107+
uint16_t current_stapm_power_limit;
1108+
1109+
/* Average clocks */
1110+
uint16_t average_gfxclk_frequency;
1111+
uint16_t average_socclk_frequency;
1112+
uint16_t average_vpeclk_frequency;
1113+
uint16_t average_ipuclk_frequency;
1114+
uint16_t average_fclk_frequency;
1115+
uint16_t average_vclk_frequency;
1116+
1117+
/* Current clocks */
1118+
/* target core frequency */
1119+
uint16_t current_coreclk[16];
1120+
/* CCLK frequency limit enforced on classic cores [MHz] */
1121+
uint16_t current_core_maxfreq;
1122+
/* GFXCLK frequency limit enforced on GFX [MHz] */
1123+
uint16_t current_gfx_maxfreq;
1124+
1125+
/* Metrics table alpha filter time constant [us] */
1126+
uint32_t time_filter_alphavalue;
1127+
};
10601128
#endif

‎drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h‎

Lines changed: 35 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -149,23 +149,37 @@ typedef struct {
149149
uint32_t MaxGfxClk;
150150
} DpmClocks_t;
151151

152-
153-
// Throttler Status Bitmask
154-
#define THROTTLER_STATUS_BIT_SPL 0
155-
#define THROTTLER_STATUS_BIT_FPPT 1
156-
#define THROTTLER_STATUS_BIT_SPPT 2
157-
#define THROTTLER_STATUS_BIT_SPPT_APU 3
158-
#define THROTTLER_STATUS_BIT_THM_CORE 4
159-
#define THROTTLER_STATUS_BIT_THM_GFX 5
160-
#define THROTTLER_STATUS_BIT_THM_SOC 6
161-
#define THROTTLER_STATUS_BIT_TDC_VDD 7
162-
#define THROTTLER_STATUS_BIT_TDC_VDDCCX 8
163-
#define THROTTLER_STATUS_BIT_TDC_SOC 9
164-
#define THROTTLER_STATUS_BIT_PROCHOT_CPU 10
165-
#define THROTTLER_STATUS_BIT_PROCHOT_GFX 11
166-
#define THROTTLER_STATUS_BIT_EDC_CPU_CLASSIC 12
167-
#define THROTTLER_STATUS_BIT_EDC_CPU_DENSE 13
168-
#define THROTTLER_STATUS_BIT_EDC_GFX 14
152+
typedef struct {
153+
uint16_t CoreFrequency[16]; //Target core frequency [MHz]
154+
uint16_t CorePower[16]; //CAC calculated core power [W] [Q8.8]
155+
uint16_t CoreTemperature[16]; //TSEN measured core temperature [C] [Q8.8]
156+
uint16_t GfxTemperature; //TSEN measured GFX temperature [C] [Q8.8]
157+
uint16_t SocTemperature; //TSEN measured SOC temperature [C] [Q8.8]
158+
uint16_t StapmOpnLimit; //Maximum IRM defined STAPM power limit [W] [Q8.8]
159+
uint16_t StapmCurrentLimit; //Time filtered STAPM power limit [W] [Q8.8]
160+
uint16_t InfrastructureCpuMaxFreq; //CCLK frequency limit enforced on classic cores [MHz]
161+
uint16_t InfrastructureGfxMaxFreq; //GFXCLK frequency limit enforced on GFX [MHz]
162+
uint16_t SkinTemp; //Maximum skin temperature reported by APU and HS2 chassis sensors [C] [Q8.8]
163+
uint16_t AverageGfxclkFrequency; //Time filtered target GFXCLK frequency [MHz]
164+
uint16_t AverageFclkFrequency; //Time filtered target FCLK frequency [MHz]
165+
uint16_t AverageGfxActivity; //Time filtered GFX busy % [0-100] [Q8.8]
166+
uint16_t AverageSocclkFrequency; //Time filtered target SOCCLK frequency [MHz]
167+
uint16_t AverageVclkFrequency; //Time filtered target VCLK frequency [MHz]
168+
uint16_t AverageVcnActivity; //Time filtered VCN busy % [0-100] [Q8.8]
169+
uint16_t AverageVpeclkFrequency; //Time filtered target VPECLK frequency [MHz]
170+
uint16_t AverageIpuclkFrequency; //Time filtered target IPUCLK frequency [MHz]
171+
uint16_t AverageIpuBusy[8]; //Time filtered IPU per-column busy % [0-100] [Q8.8]
172+
uint16_t AverageDRAMReads; //Time filtered DRAM read bandwidth [GB/sec] [Q8.8]
173+
uint16_t AverageDRAMWrites; //Time filtered DRAM write bandwidth [GB/sec] [Q8.8]
174+
uint16_t AverageCoreC0Residency[16]; //Time filtered per-core C0 residency % [0-100] [Q8.8]
175+
uint16_t IpuPower; //Time filtered IPU power [W] [Q8.8]
176+
uint32_t ApuPower; //Time filtered APU power [W] [Q24.8]
177+
uint32_t dGpuPower; //Time filtered dGPU power [W] [Q24.8]
178+
uint32_t AverageSocketPower; //Time filtered power used for PPT/STAPM [APU+dGPU] [W] [Q24.8]
179+
uint32_t AverageCorePower; //Time filtered sum of core power across all cores in the socket [W] [Q24.8]
180+
uint32_t FilterAlphaValue; //Metrics table alpha filter time constant [us]
181+
uint32_t MetricsCounter; //Counter that is incremented on every metrics table update [PM_TIMER cycles]
182+
} SmuMetrics_t;
169183

170184
typedef struct {
171185
uint16_t GfxclkFrequency; //[MHz]
@@ -212,7 +226,6 @@ typedef struct {
212226
uint16_t CurTemp; //[centi-Celsius]
213227
uint16_t FilterAlphaValue; //[m]
214228

215-
//PMFW-8735
216229
uint16_t AverageGfxclkFrequency;
217230
uint16_t AverageFclkFrequency;
218231
uint16_t AverageGfxActivity;
@@ -224,20 +237,9 @@ typedef struct {
224237
uint16_t AverageSocketPower; //Filtered value of CurrentSocketPower
225238
uint16_t AverageCorePower[2]; //Filtered of [sum of CorePower[8] per ccx])
226239
uint16_t AverageCoreC0Residency[16]; //Filtered of [average C0 residency % per core]
227-
uint16_t spare3;
240+
uint16_t spare1;
228241
uint32_t MetricsCounter; //Counts the # of metrics table parameter reads per update to the metrics table, i.e. if the metrics table update happens every 1 second, this value could be up to 1000 if the smu collected metrics data every cycle, or as low as 0 if the smu was asleep the whole time. Reset to 0 after writing.
229-
} SmuMetrics_t;
230-
231-
typedef struct {
232-
uint16_t StapmMaxPlatformLimit; //[W]
233-
uint16_t StapmMinPlatformLimit; //[W]
234-
uint16_t FastPptMaxPlatformLimit; //[W]
235-
uint16_t FastPptMinPlatformLimit; //[W]
236-
uint16_t SlowPptMaxPlatformLimit; //[W]
237-
uint16_t SlowPptMinPlatformLimit; //[W]
238-
uint16_t SlowPptApuMaxPlatformLimit; //[W]
239-
uint16_t SlowPptApuMinPlatformLimit; //[W]
240-
} PmfInfo_t;
242+
} SmuMetrics_legacy_t;
241243

242244
//ISP tile definitions
243245
typedef enum {
@@ -272,10 +274,9 @@ typedef enum {
272274
#define TABLE_CUSTOM_DPM 2 // Called by Driver
273275
#define TABLE_BIOS_GPIO_CONFIG 3 // Called by BIOS
274276
#define TABLE_DPMCLOCKS 4 // Called by Driver and VBIOS
275-
#define TABLE_MOMENTARY_PM 5 // Called by Tools
277+
#define TABLE_SPARE0 5 // Unused
276278
#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
277279
#define TABLE_SMU_METRICS 7 // Called by Driver and SMF/PMF
278-
#define TABLE_INFRASTRUCTURE_LIMITS 8 // Called by SMF/PMF
279-
#define TABLE_COUNT 9
280+
#define TABLE_COUNT 8
280281

281282
#endif

‎drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h‎

Lines changed: 15 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -58,43 +58,43 @@
5858
#define FEATURE_DS_LCLK_BIT 23
5959
#define FEATURE_LOW_POWER_DCNCLKS_BIT 24 // for all DISP clks
6060
#define FEATURE_DS_SHUBCLK_BIT 25
61-
#define FEATURE_GFX_TEMP_VMIN_BIT 26
61+
#define FEATURE_SPARE0_BIT 26 //SPARE
6262
#define FEATURE_ZSTATES_BIT 27
6363
#define FEATURE_IOMMUL2_PG_BIT 28
6464
#define FEATURE_DS_FCLK_BIT 29
6565
#define FEATURE_DS_SMNCLK_BIT 30
6666
#define FEATURE_DS_MP1CLK_BIT 31
67-
#define FEATURE_RESERVED3 32
67+
#define FEATURE_WHISPER_MODE_BIT 32
6868
#define FEATURE_SMU_LOW_POWER_BIT 33
6969
#define FEATURE_SMART_L3_RINSER_BIT 34
70-
#define FEATURE_GFX_DEM_BIT 35
70+
#define FEATURE_SPARE1_BIT 35 //SPARE
7171
#define FEATURE_PSI_BIT 36
7272
#define FEATURE_PROCHOT_BIT 37
7373
#define FEATURE_CPUOFF_BIT 38
7474
#define FEATURE_STAPM_BIT 39
7575
#define FEATURE_S0I3_BIT 40
76-
#define FEATURE_DF_LIGHT_CSTATE 41 // shift the order or DFCstate annd DF light Cstate
76+
#define FEATURE_DF_LIGHT_CSTATE 41
7777
#define FEATURE_PERF_LIMIT_BIT 42
7878
#define FEATURE_CORE_DLDO_BIT 43
7979
#define FEATURE_DVO_BIT 44
8080
#define FEATURE_DS_VCN_BIT 45
8181
#define FEATURE_CPPC_BIT 46
8282
#define FEATURE_CPPC_PREFERRED_CORES 47
8383
#define FEATURE_DF_CSTATES_BIT 48
84-
#define FEATURE_RESERVED4 49
84+
#define FEATURE_SPARE2_BIT 49 //SPARE
8585
#define FEATURE_ATHUB_PG_BIT 50
8686
#define FEATURE_VDDOFF_ECO_BIT 51
8787
#define FEATURE_ZSTATES_ECO_BIT 52
8888
#define FEATURE_CC6_BIT 53
8989
#define FEATURE_DS_UMCCLK_BIT 54
9090
#define FEATURE_DS_ISPCLK_BIT 55
9191
#define FEATURE_DS_HSPCLK_BIT 56
92-
#define FEATURE_RESERVED5 57
92+
#define FEATURE_P3T_BIT 57
9393
#define FEATURE_DS_IPUCLK_BIT 58
9494
#define FEATURE_DS_VPECLK_BIT 59
9595
#define FEATURE_VPE_DPM_BIT 60
96-
#define FEATURE_BABYPHASE_SVI3_BIT 61
97-
#define FEATURE_FP_DIDT_BIT 62
96+
#define FEATURE_SPARE_61 61
97+
#define FEATURE_FP_DIDT 62
9898
#define NUM_FEATURES 63
9999

100100
// Firmware Header/Footer
@@ -123,12 +123,13 @@ typedef struct {
123123
uint32_t DpmHubTask : 4;
124124
// MP1_EXT_SCRATCH1
125125
uint32_t CclkSyncStatus : 8;
126+
uint32_t Ccx0CpuOff : 2;
127+
uint32_t Ccx1CpuOff : 2;
126128
uint32_t GfxOffStatus : 2;
127-
uint32_t CpuOff : 2;
128129
uint32_t VddOff : 1;
129-
uint32_t spare0 : 3;
130+
uint32_t InWhisperMode : 1;
130131
uint32_t ZstateStatus : 4;
131-
uint32_t spare1 : 4;
132+
uint32_t spare0 : 4;
132133
uint32_t DstateFun : 4;
133134
uint32_t DstateDev : 4;
134135
// MP1_EXT_SCRATCH2
@@ -140,10 +141,10 @@ typedef struct {
140141
uint32_t MsgPortBusy :24;
141142
uint32_t RsmuPmiP1Pending : 1;
142143
uint32_t DfCstateExitPending : 1;
143-
uint32_t Pc6EntryPending : 1;
144-
uint32_t Pc6ExitPending : 1;
144+
uint32_t Ccx0Pc6ExitPending : 1;
145+
uint32_t Ccx1Pc6ExitPending : 1;
145146
uint32_t WarmResetPending : 1;
146-
uint32_t spare2 : 3;
147+
uint32_t spare1 : 3;
147148
// MP1_EXT_SCRATCH5
148149
uint32_t IdleMask :32;
149150
// MP1_EXT_SCRATCH6 = RTOS threads' status

‎drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_ppsmc.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -75,8 +75,8 @@
7575

7676
#define PPSMC_MSG_EnableGfxImu 0x16 ///< Enable GFX IMU
7777

78-
#define PPSMC_MSG_GetGfxclkFrequency 0x17 ///< Get GFX clock frequency
79-
#define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
78+
#define PPSMC_MSG_spare_0x17 0x17
79+
#define PPSMC_MSG_spare_0x18 0x18
8080
#define PPSMC_MSG_AllowGfxOff 0x19 ///< Inform PMFW of allowing GFXOFF entry
8181
#define PPSMC_MSG_DisallowGfxOff 0x1A ///< Inform PMFW of disallowing GFXOFF entry
8282
#define PPSMC_MSG_SetSoftMaxGfxClk 0x1B ///< Set soft max for GFX CLK
@@ -85,6 +85,7 @@
8585
#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x1D ///< Set soft max for SOC CLK
8686
#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK
8787
#define PPSMC_MSG_SetSoftMaxVcn 0x1F ///< Set soft max for VCN clocks (VCLK and DCLK)
88+
#define PPSMC_MSG_spare_0x20 0x20
8889
#define PPSMC_MSG_PowerDownJpeg 0x21 ///< Power down Jpeg
8990
#define PPSMC_MSG_PowerUpJpeg 0x22 ///< Power up Jpeg; VCN is power gated by default
9091

‎drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -422,7 +422,8 @@ enum smu_clk_type {
422422
__SMU_DUMMY_MAP(ATHUB_MMHUB_PG), \
423423
__SMU_DUMMY_MAP(BACO_CG), \
424424
__SMU_DUMMY_MAP(SOC_CG), \
425-
__SMU_DUMMY_MAP(LOW_POWER_DCNCLKS),
425+
__SMU_DUMMY_MAP(LOW_POWER_DCNCLKS), \
426+
__SMU_DUMMY_MAP(WHISPER_MODE),
426427

427428
#undef __SMU_DUMMY_MAP
428429
#define __SMU_DUMMY_MAP(feature) SMU_FEATURE_##feature##_BIT

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