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AngeloGioacchino Del Regnodlezcano
AngeloGioacchino Del Regno
authored and
dlezcano
committed
clocksource/drivers/timer-mediatek: Split out CPUXGPT timers
On MediaTek platforms, CPUXGPT is the source for the AArch64 System Timer, read through CNTVCT_EL0. The handling for starting this timer ASAP was introduced in commit 327e93c ("clocksource/drivers/timer-mediatek: Implement CPUXGPT timers") which description also contains an important full explanation of the reasons why this driver is necessary and cannot be a module. In preparation for an eventual conversion of timer-mediatek to a platform_driver that would be possibly built as a module, split out the CPUXGPT timers driver to a new timer-mediatek-cpux.c driver. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Walter Chang <walter.chang@mediatek.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20230309103913.116775-1-angelogioacchino.delregno@collabora.com
1 parent fd3f088 commit 49d576e

4 files changed

Lines changed: 150 additions & 114 deletions

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‎drivers/clocksource/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -479,6 +479,15 @@ config MTK_TIMER
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help
480480
Support for Mediatek timer driver.
481481

482+
config MTK_CPUX_TIMER
483+
bool "MediaTek CPUX timer driver" if COMPILE_TEST
484+
depends on HAS_IOMEM
485+
default ARCH_MEDIATEK
486+
select TIMER_OF
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select CLKSRC_MMIO
488+
help
489+
Support for MediaTek CPUXGPT timer driver.
490+
482491
config SPRD_TIMER
483492
bool "Spreadtrum timer driver" if EXPERT
484493
depends on HAS_IOMEM

‎drivers/clocksource/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,7 @@ obj-$(CONFIG_FSL_FTM_TIMER) += timer-fsl-ftm.o
5151
obj-$(CONFIG_VF_PIT_TIMER) += timer-vf-pit.o
5252
obj-$(CONFIG_CLKSRC_QCOM) += timer-qcom.o
5353
obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o
54+
obj-$(CONFIG_MTK_CPUX_TIMER) += timer-mediatek-cpux.o
5455
obj-$(CONFIG_CLKSRC_PISTACHIO) += timer-pistachio.o
5556
obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
5657
obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o

‎drivers/clocksource/timer-mediatek-cpux.c‎

Lines changed: 140 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,140 @@
1+
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MediaTek SoCs CPUX General Purpose Timer handling
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*
5+
* Based on timer-mediatek.c:
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* Copyright (C) 2014 Matthias Brugger <matthias.bgg@gmail.com>
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*
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* Copyright (C) 2022 Collabora Ltd.
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
11+
12+
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13+
14+
#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/interrupt.h>
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#include <linux/irqreturn.h>
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#include <linux/sched_clock.h>
19+
#include <linux/slab.h>
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#include "timer-of.h"
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22+
#define TIMER_SYNC_TICKS 3
23+
24+
/* cpux mcusys wrapper */
25+
#define CPUX_CON_REG 0x0
26+
#define CPUX_IDX_REG 0x4
27+
28+
/* cpux */
29+
#define CPUX_IDX_GLOBAL_CTRL 0x0
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#define CPUX_ENABLE BIT(0)
31+
#define CPUX_CLK_DIV_MASK GENMASK(10, 8)
32+
#define CPUX_CLK_DIV1 BIT(8)
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#define CPUX_CLK_DIV2 BIT(9)
34+
#define CPUX_CLK_DIV4 BIT(10)
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#define CPUX_IDX_GLOBAL_IRQ 0x30
36+
37+
static u32 mtk_cpux_readl(u32 reg_idx, struct timer_of *to)
38+
{
39+
writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
40+
return readl(timer_of_base(to) + CPUX_CON_REG);
41+
}
42+
43+
static void mtk_cpux_writel(u32 val, u32 reg_idx, struct timer_of *to)
44+
{
45+
writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
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writel(val, timer_of_base(to) + CPUX_CON_REG);
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}
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49+
static void mtk_cpux_set_irq(struct timer_of *to, bool enable)
50+
{
51+
const unsigned long *irq_mask = cpumask_bits(cpu_possible_mask);
52+
u32 val;
53+
54+
val = mtk_cpux_readl(CPUX_IDX_GLOBAL_IRQ, to);
55+
56+
if (enable)
57+
val |= *irq_mask;
58+
else
59+
val &= ~(*irq_mask);
60+
61+
mtk_cpux_writel(val, CPUX_IDX_GLOBAL_IRQ, to);
62+
}
63+
64+
static int mtk_cpux_clkevt_shutdown(struct clock_event_device *clkevt)
65+
{
66+
/* Clear any irq */
67+
mtk_cpux_set_irq(to_timer_of(clkevt), false);
68+
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/*
70+
* Disabling CPUXGPT timer will crash the platform, especially
71+
* if Trusted Firmware is using it (usually, for sleep states),
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* so we only mask the IRQ and call it a day.
73+
*/
74+
return 0;
75+
}
76+
77+
static int mtk_cpux_clkevt_resume(struct clock_event_device *clkevt)
78+
{
79+
mtk_cpux_set_irq(to_timer_of(clkevt), true);
80+
return 0;
81+
}
82+
83+
static struct timer_of to = {
84+
/*
85+
* There are per-cpu interrupts for the CPUX General Purpose Timer
86+
* but since this timer feeds the AArch64 System Timer we can rely
87+
* on the CPU timer PPIs as well, so we don't declare TIMER_OF_IRQ.
88+
*/
89+
.flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
90+
91+
.clkevt = {
92+
.name = "mtk-cpuxgpt",
93+
.cpumask = cpu_possible_mask,
94+
.rating = 10,
95+
.set_state_shutdown = mtk_cpux_clkevt_shutdown,
96+
.tick_resume = mtk_cpux_clkevt_resume,
97+
},
98+
};
99+
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static int __init mtk_cpux_init(struct device_node *node)
101+
{
102+
u32 freq, val;
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int ret;
104+
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/* If this fails, bad things are about to happen... */
106+
ret = timer_of_init(node, &to);
107+
if (ret) {
108+
WARN(1, "Cannot start CPUX timers.\n");
109+
return ret;
110+
}
111+
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/*
113+
* Check if we're given a clock with the right frequency for this
114+
* timer, otherwise warn but keep going with the setup anyway, as
115+
* that makes it possible to still boot the kernel, even though
116+
* it may not work correctly (random lockups, etc).
117+
* The reason behind this is that having an early UART may not be
118+
* possible for everyone and this gives a chance to retrieve kmsg
119+
* for eventual debugging even on consumer devices.
120+
*/
121+
freq = timer_of_rate(&to);
122+
if (freq > 13000000)
123+
WARN(1, "Requested unsupported timer frequency %u\n", freq);
124+
125+
/* Clock input is 26MHz, set DIV2 to achieve 13MHz clock */
126+
val = mtk_cpux_readl(CPUX_IDX_GLOBAL_CTRL, &to);
127+
val &= ~CPUX_CLK_DIV_MASK;
128+
val |= CPUX_CLK_DIV2;
129+
mtk_cpux_writel(val, CPUX_IDX_GLOBAL_CTRL, &to);
130+
131+
/* Enable all CPUXGPT timers */
132+
val = mtk_cpux_readl(CPUX_IDX_GLOBAL_CTRL, &to);
133+
mtk_cpux_writel(val | CPUX_ENABLE, CPUX_IDX_GLOBAL_CTRL, &to);
134+
135+
clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
136+
TIMER_SYNC_TICKS, 0xffffffff);
137+
138+
return 0;
139+
}
140+
TIMER_OF_DECLARE(mtk_mt6795, "mediatek,mt6795-systimer", mtk_cpux_init);

‎drivers/clocksource/timer-mediatek.c‎

Lines changed: 0 additions & 114 deletions
Original file line numberDiff line numberDiff line change
@@ -22,19 +22,6 @@
2222

2323
#define TIMER_SYNC_TICKS (3)
2424

25-
/* cpux mcusys wrapper */
26-
#define CPUX_CON_REG 0x0
27-
#define CPUX_IDX_REG 0x4
28-
29-
/* cpux */
30-
#define CPUX_IDX_GLOBAL_CTRL 0x0
31-
#define CPUX_ENABLE BIT(0)
32-
#define CPUX_CLK_DIV_MASK GENMASK(10, 8)
33-
#define CPUX_CLK_DIV1 BIT(8)
34-
#define CPUX_CLK_DIV2 BIT(9)
35-
#define CPUX_CLK_DIV4 BIT(10)
36-
#define CPUX_IDX_GLOBAL_IRQ 0x30
37-
3825
/* gpt */
3926
#define GPT_IRQ_EN_REG 0x00
4027
#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
@@ -85,52 +72,6 @@
8572

8673
static void __iomem *gpt_sched_reg __read_mostly;
8774

88-
static u32 mtk_cpux_readl(u32 reg_idx, struct timer_of *to)
89-
{
90-
writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
91-
return readl(timer_of_base(to) + CPUX_CON_REG);
92-
}
93-
94-
static void mtk_cpux_writel(u32 val, u32 reg_idx, struct timer_of *to)
95-
{
96-
writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
97-
writel(val, timer_of_base(to) + CPUX_CON_REG);
98-
}
99-
100-
static void mtk_cpux_set_irq(struct timer_of *to, bool enable)
101-
{
102-
const unsigned long *irq_mask = cpumask_bits(cpu_possible_mask);
103-
u32 val;
104-
105-
val = mtk_cpux_readl(CPUX_IDX_GLOBAL_IRQ, to);
106-
107-
if (enable)
108-
val |= *irq_mask;
109-
else
110-
val &= ~(*irq_mask);
111-
112-
mtk_cpux_writel(val, CPUX_IDX_GLOBAL_IRQ, to);
113-
}
114-
115-
static int mtk_cpux_clkevt_shutdown(struct clock_event_device *clkevt)
116-
{
117-
/* Clear any irq */
118-
mtk_cpux_set_irq(to_timer_of(clkevt), false);
119-
120-
/*
121-
* Disabling CPUXGPT timer will crash the platform, especially
122-
* if Trusted Firmware is using it (usually, for sleep states),
123-
* so we only mask the IRQ and call it a day.
124-
*/
125-
return 0;
126-
}
127-
128-
static int mtk_cpux_clkevt_resume(struct clock_event_device *clkevt)
129-
{
130-
mtk_cpux_set_irq(to_timer_of(clkevt), true);
131-
return 0;
132-
}
133-
13475
static void mtk_syst_ack_irq(struct timer_of *to)
13576
{
13677
/* Clear and disable interrupt */
@@ -340,60 +281,6 @@ static struct timer_of to = {
340281
},
341282
};
342283

343-
static int __init mtk_cpux_init(struct device_node *node)
344-
{
345-
static struct timer_of to_cpux;
346-
u32 freq, val;
347-
int ret;
348-
349-
/*
350-
* There are per-cpu interrupts for the CPUX General Purpose Timer
351-
* but since this timer feeds the AArch64 System Timer we can rely
352-
* on the CPU timer PPIs as well, so we don't declare TIMER_OF_IRQ.
353-
*/
354-
to_cpux.flags = TIMER_OF_BASE | TIMER_OF_CLOCK;
355-
to_cpux.clkevt.name = "mtk-cpuxgpt";
356-
to_cpux.clkevt.rating = 10;
357-
to_cpux.clkevt.cpumask = cpu_possible_mask;
358-
to_cpux.clkevt.set_state_shutdown = mtk_cpux_clkevt_shutdown;
359-
to_cpux.clkevt.tick_resume = mtk_cpux_clkevt_resume;
360-
361-
/* If this fails, bad things are about to happen... */
362-
ret = timer_of_init(node, &to_cpux);
363-
if (ret) {
364-
WARN(1, "Cannot start CPUX timers.\n");
365-
return ret;
366-
}
367-
368-
/*
369-
* Check if we're given a clock with the right frequency for this
370-
* timer, otherwise warn but keep going with the setup anyway, as
371-
* that makes it possible to still boot the kernel, even though
372-
* it may not work correctly (random lockups, etc).
373-
* The reason behind this is that having an early UART may not be
374-
* possible for everyone and this gives a chance to retrieve kmsg
375-
* for eventual debugging even on consumer devices.
376-
*/
377-
freq = timer_of_rate(&to_cpux);
378-
if (freq > 13000000)
379-
WARN(1, "Requested unsupported timer frequency %u\n", freq);
380-
381-
/* Clock input is 26MHz, set DIV2 to achieve 13MHz clock */
382-
val = mtk_cpux_readl(CPUX_IDX_GLOBAL_CTRL, &to_cpux);
383-
val &= ~CPUX_CLK_DIV_MASK;
384-
val |= CPUX_CLK_DIV2;
385-
mtk_cpux_writel(val, CPUX_IDX_GLOBAL_CTRL, &to_cpux);
386-
387-
/* Enable all CPUXGPT timers */
388-
val = mtk_cpux_readl(CPUX_IDX_GLOBAL_CTRL, &to_cpux);
389-
mtk_cpux_writel(val | CPUX_ENABLE, CPUX_IDX_GLOBAL_CTRL, &to_cpux);
390-
391-
clockevents_config_and_register(&to_cpux.clkevt, timer_of_rate(&to_cpux),
392-
TIMER_SYNC_TICKS, 0xffffffff);
393-
394-
return 0;
395-
}
396-
397284
static int __init mtk_syst_init(struct device_node *node)
398285
{
399286
int ret;
@@ -452,4 +339,3 @@ static int __init mtk_gpt_init(struct device_node *node)
452339
}
453340
TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
454341
TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init);
455-
TIMER_OF_DECLARE(mtk_mt6795, "mediatek,mt6795-systimer", mtk_cpux_init);

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