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bjdooks-ctthierryreding
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pwm: dwc: add PWM bit unset in get_state call
If we are not in PWM mode, then the output is technically a 50% output based on a single timer instead of the high-low based on the two counters. Add a check for the PWM mode in dwc_pwm_get_state() and if DWC_TIM_CTRL_PWM is not set, then return a 50% cycle. This may only be an issue on initialisation, as the rest of the code currently assumes we're always going to have the extended PWM mode using two counters. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230907161242.67190-4-ben.dooks@codethink.co.uk Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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Lines changed: 19 additions & 11 deletions

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drivers/pwm/pwm-dwc-core.c

Lines changed: 19 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -122,24 +122,32 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
122122
{
123123
struct dwc_pwm *dwc = to_dwc_pwm(chip);
124124
u64 duty, period;
125+
u32 ctrl, ld, ld2;
125126

126127
pm_runtime_get_sync(chip->dev);
127128

128-
state->enabled = !!(dwc_pwm_readl(dwc,
129-
DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN);
129+
ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm));
130+
ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm));
131+
ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));
130132

131-
duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm));
132-
duty += 1;
133-
duty *= dwc->clk_ns;
134-
state->duty_cycle = duty;
133+
state->enabled = !!(ctrl & DWC_TIM_CTRL_EN);
135134

136-
period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));
137-
period += 1;
138-
period *= dwc->clk_ns;
139-
period += duty;
140-
state->period = period;
135+
/*
136+
* If we're not in PWM, technically the output is a 50-50
137+
* based on the timer load-count only.
138+
*/
139+
if (ctrl & DWC_TIM_CTRL_PWM) {
140+
duty = (ld + 1) * dwc->clk_ns;
141+
period = (ld2 + 1) * dwc->clk_ns;
142+
period += duty;
143+
} else {
144+
duty = (ld + 1) * dwc->clk_ns;
145+
period = duty * 2;
146+
}
141147

142148
state->polarity = PWM_POLARITY_INVERSED;
149+
state->period = period;
150+
state->duty_cycle = duty;
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144152
pm_runtime_put_sync(chip->dev);
145153

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