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petegriffinkrzk
petegriffin
authored and
krzk
committed
clk: samsung: gs101: add support for Display Process Unit (DPU) clocks
cmu_dpu is the clock management unit used for the Display Process Unit block. It generates clocks for image scaler, compressor etc. Add support for the muxes, dividers and gates in cmu_dpu. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Link: https://patch.msgid.link/20260113-dpu-clocks-v3-4-cb85424f2c72@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
1 parent 1d8fae6 commit 4b18a3e

1 file changed

Lines changed: 283 additions & 0 deletions

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‎drivers/clk/samsung/clk-gs101.c‎

Lines changed: 283 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020
/* NOTE: Must be equal to the last clock ID increased by one */
2121
#define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1)
2222
#define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1)
23+
#define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_DPU_PCLK + 1)
2324
#define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_P_HSI0_ACLK + 1)
2425
#define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1)
2526
#define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
@@ -1932,6 +1933,285 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
19321933
.memclk_offset = GS101_MEMCLK_OFFSET,
19331934
};
19341935

1936+
/* ---- CMU_DPU ------------------------------------------------------------- */
1937+
1938+
/* Register Offset definitions for CMU_DPU (0x1c000000) */
1939+
#define PLL_CON0_MUX_CLKCMU_DPU_BUS_USER 0x0600
1940+
#define PLL_CON1_MUX_CLKCMU_DPU_BUS_USER 0x0604
1941+
#define DPU_CMU_DPU_CONTROLLER_OPTION 0x0800
1942+
#define CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0 0x0810
1943+
#define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800
1944+
#define CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK 0x2000
1945+
#define CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK 0x2004
1946+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM 0x2008
1947+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA 0x200c
1948+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP 0x2010
1949+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK 0x2014
1950+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK 0x2018
1951+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK 0x201c
1952+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK 0x2020
1953+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK 0x2024
1954+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK 0x2028
1955+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK 0x202c
1956+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK 0x2030
1957+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK 0x2034
1958+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK 0x2038
1959+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK 0x203c
1960+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK 0x2040
1961+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK 0x2044
1962+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK 0x2048
1963+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK 0x204c
1964+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK 0x2050
1965+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK 0x2054
1966+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK 0x2058
1967+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK 0x205c
1968+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK 0x2060
1969+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1 0x2064
1970+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2 0x2068
1971+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1 0x206c
1972+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2 0x2070
1973+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1 0x2074
1974+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2 0x2078
1975+
#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK 0x207c
1976+
#define PCH_CON_LHM_AXI_P_DPU_PCH 0x3000
1977+
#define PCH_CON_LHS_AXI_D0_DPU_PCH 0x3004
1978+
#define PCH_CON_LHS_AXI_D1_DPU_PCH 0x3008
1979+
#define PCH_CON_LHS_AXI_D2_DPU_PCH 0x300c
1980+
#define QCH_CON_DPUF_QCH_DPU_DMA 0x3010
1981+
#define QCH_CON_DPUF_QCH_DPU_DPP 0x3014
1982+
#define QCH_CON_DPU_CMU_DPU_QCH 0x301c
1983+
#define QCH_CON_D_TZPC_DPU_QCH 0x3020
1984+
#define QCH_CON_GPC_DPU_QCH 0x3024
1985+
#define QCH_CON_LHM_AXI_P_DPU_QCH 0x3028
1986+
#define QCH_CON_LHS_AXI_D0_DPU_QCH 0x302c
1987+
#define QCH_CON_LHS_AXI_D1_DPU_QCH 0x3030
1988+
#define QCH_CON_LHS_AXI_D2_DPU_QCH 0x3034
1989+
#define QCH_CON_PPMU_DPUD0_QCH 0x3038
1990+
#define QCH_CON_PPMU_DPUD1_QCH 0x303c
1991+
#define QCH_CON_PPMU_DPUD2_QCH 0x3040
1992+
#define QCH_CON_SSMT_DPU0_QCH 0x3044
1993+
#define QCH_CON_SSMT_DPU1_QCH 0x3048
1994+
#define QCH_CON_SSMT_DPU2_QCH 0x304c
1995+
#define QCH_CON_SYSMMU_DPUD0_QCH_S1 0x3050
1996+
#define QCH_CON_SYSMMU_DPUD0_QCH_S2 0x3054
1997+
#define QCH_CON_SYSMMU_DPUD1_QCH_S1 0x3058
1998+
#define QCH_CON_SYSMMU_DPUD1_QCH_S2 0x305c
1999+
#define QCH_CON_SYSMMU_DPUD2_QCH_S1 0x3060
2000+
#define QCH_CON_SYSMMU_DPUD2_QCH_S2 0x3064
2001+
#define QCH_CON_SYSREG_DPU_QCH 0x3068
2002+
#define QUEUE_CTRL_REG_BLK_DPU_CMU_DPU 0x3c00
2003+
2004+
static const unsigned long dpu_clk_regs[] __initconst = {
2005+
PLL_CON0_MUX_CLKCMU_DPU_BUS_USER,
2006+
PLL_CON1_MUX_CLKCMU_DPU_BUS_USER,
2007+
DPU_CMU_DPU_CONTROLLER_OPTION,
2008+
CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0,
2009+
CLK_CON_DIV_DIV_CLK_DPU_BUSP,
2010+
CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK,
2011+
CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK,
2012+
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM,
2013+
CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA,
2014+
CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP,
2015+
CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK,
2016+
CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK,
2017+
CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK,
2018+
CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK,
2019+
CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK,
2020+
CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK,
2021+
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK,
2022+
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK,
2023+
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK,
2024+
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK,
2025+
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK,
2026+
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK,
2027+
CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK,
2028+
CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK,
2029+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK,
2030+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK,
2031+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK,
2032+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK,
2033+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK,
2034+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK,
2035+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1,
2036+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2,
2037+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1,
2038+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2,
2039+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1,
2040+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2,
2041+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK,
2042+
PCH_CON_LHM_AXI_P_DPU_PCH,
2043+
PCH_CON_LHS_AXI_D0_DPU_PCH,
2044+
PCH_CON_LHS_AXI_D1_DPU_PCH,
2045+
PCH_CON_LHS_AXI_D2_DPU_PCH,
2046+
QCH_CON_DPUF_QCH_DPU_DMA,
2047+
QCH_CON_DPUF_QCH_DPU_DPP,
2048+
QCH_CON_DPU_CMU_DPU_QCH,
2049+
QCH_CON_D_TZPC_DPU_QCH,
2050+
QCH_CON_GPC_DPU_QCH,
2051+
QCH_CON_LHM_AXI_P_DPU_QCH,
2052+
QCH_CON_LHS_AXI_D0_DPU_QCH,
2053+
QCH_CON_LHS_AXI_D1_DPU_QCH,
2054+
QCH_CON_LHS_AXI_D2_DPU_QCH,
2055+
QCH_CON_PPMU_DPUD0_QCH,
2056+
QCH_CON_PPMU_DPUD1_QCH,
2057+
QCH_CON_PPMU_DPUD2_QCH,
2058+
QCH_CON_SSMT_DPU0_QCH,
2059+
QCH_CON_SSMT_DPU1_QCH,
2060+
QCH_CON_SSMT_DPU2_QCH,
2061+
QCH_CON_SYSMMU_DPUD0_QCH_S1,
2062+
QCH_CON_SYSMMU_DPUD0_QCH_S2,
2063+
QCH_CON_SYSMMU_DPUD1_QCH_S1,
2064+
QCH_CON_SYSMMU_DPUD1_QCH_S2,
2065+
QCH_CON_SYSMMU_DPUD2_QCH_S1,
2066+
QCH_CON_SYSMMU_DPUD2_QCH_S2,
2067+
QCH_CON_SYSREG_DPU_QCH,
2068+
QUEUE_CTRL_REG_BLK_DPU_CMU_DPU,
2069+
};
2070+
2071+
/* List of parent clocks for Muxes in CMU_DPU */
2072+
PNAME(mout_dpu_bus_user_p) = { "oscclk", "dout_cmu_dpu_bus" };
2073+
2074+
static const struct samsung_mux_clock dpu_mux_clks[] __initconst = {
2075+
MUX(CLK_MOUT_DPU_BUS_USER, "mout_dpu_bus_user",
2076+
mout_dpu_bus_user_p, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER, 4, 1),
2077+
};
2078+
2079+
static const struct samsung_div_clock dpu_div_clks[] __initconst = {
2080+
DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_bus_user",
2081+
CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3),
2082+
};
2083+
2084+
static const struct samsung_gate_clock dpu_gate_clks[] __initconst = {
2085+
GATE(CLK_GOUT_DPU_PCLK, "gout_dpu_dpu_pclk",
2086+
"dout_dpu_busp",
2087+
CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK, 21, 0, 0),
2088+
GATE(CLK_GOUT_DPU_CLK_DPU_OSCCLK_CLK, "gout_dpu_clk_dpu_oscclk_clk",
2089+
"oscclk",
2090+
CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK,
2091+
21, 0, 0),
2092+
GATE(CLK_GOUT_DPU_AD_APB_DPU_DMA_PCLKM, "gout_dpu_ad_apb_dpu_dma_pclkm",
2093+
"mout_dpu_bus_user",
2094+
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM,
2095+
21, 0, 0),
2096+
GATE(CLK_GOUT_DPU_DPUF_ACLK_DMA, "gout_dpu_dpuf_aclk_dma",
2097+
"mout_dpu_bus_user",
2098+
CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA, 21, 0, 0),
2099+
GATE(CLK_GOUT_DPU_DPUF_ACLK_DPP, "gout_dpu_dpuf_aclk_dpp",
2100+
"mout_dpu_bus_user",
2101+
CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP, 21, 0, 0),
2102+
GATE(CLK_GOUT_DPU_D_TZPC_DPU_PCLK, "gout_dpu_d_tzpc_dpu_pclk",
2103+
"dout_dpu_busp",
2104+
CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK, 21, 0, 0),
2105+
GATE(CLK_GOUT_DPU_GPC_DPU_PCLK, "gout_dpu_gpc_dpu_pclk",
2106+
"dout_dpu_busp",
2107+
CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK, 21, 0, 0),
2108+
GATE(CLK_GOUT_DPU_LHM_AXI_P_DPU_I_CLK, "gout_dpu_lhm_axi_p_dpu_i_clk",
2109+
"dout_dpu_busp",
2110+
CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK,
2111+
21, 0, 0),
2112+
GATE(CLK_GOUT_DPU_LHS_AXI_D0_DPU_I_CLK, "gout_dpu_lhs_axi_d0_dpu_i_clk",
2113+
"mout_dpu_bus_user",
2114+
CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK,
2115+
21, 0, 0),
2116+
GATE(CLK_GOUT_DPU_LHS_AXI_D1_DPU_I_CLK, "gout_dpu_lhs_axi_d1_dpu_i_clk",
2117+
"mout_dpu_bus_user",
2118+
CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK,
2119+
21, 0, 0),
2120+
GATE(CLK_GOUT_DPU_LHS_AXI_D2_DPU_I_CLK, "gout_dpu_lhs_axi_d2_dpu_i_clk",
2121+
"mout_dpu_bus_user",
2122+
CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK,
2123+
21, 0, 0),
2124+
GATE(CLK_GOUT_DPU_PPMU_DPUD0_ACLK, "gout_dpu_ppmu_dpud0_aclk",
2125+
"mout_dpu_bus_user",
2126+
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK, 21, 0, 0),
2127+
GATE(CLK_GOUT_DPU_PPMU_DPUD0_PCLK, "gout_dpu_ppmu_dpud0_pclk",
2128+
"dout_dpu_busp",
2129+
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK, 21, 0, 0),
2130+
GATE(CLK_GOUT_DPU_PPMU_DPUD1_ACLK, "gout_dpu_ppmu_dpud1_aclk",
2131+
"mout_dpu_bus_user",
2132+
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK, 21, 0, 0),
2133+
GATE(CLK_GOUT_DPU_PPMU_DPUD1_PCLK, "gout_dpu_ppmu_dpud1_pclk",
2134+
"dout_dpu_busp",
2135+
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK, 21, 0, 0),
2136+
GATE(CLK_GOUT_DPU_PPMU_DPUD2_ACLK, "gout_dpu_ppmu_dpud2_aclk",
2137+
"mout_dpu_bus_user",
2138+
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK, 21, 0, 0),
2139+
GATE(CLK_GOUT_DPU_PPMU_DPUD2_PCLK, "gout_dpu_ppmu_dpud2_pclk",
2140+
"dout_dpu_busp",
2141+
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK, 21, 0, 0),
2142+
GATE(CLK_GOUT_DPU_CLK_DPU_BUSD_CLK, "gout_dpu_clk_dpu_busd_clk",
2143+
"mout_dpu_bus_user",
2144+
CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK,
2145+
21, 0, 0),
2146+
GATE(CLK_GOUT_DPU_CLK_DPU_BUSP_CLK, "gout_dpu_clk_dpu_busp_clk",
2147+
"dout_dpu_busp",
2148+
CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK,
2149+
21, 0, 0),
2150+
GATE(CLK_GOUT_DPU_SSMT_DPU0_ACLK, "gout_dpu_ssmt_dpu0_aclk",
2151+
"mout_dpu_bus_user",
2152+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK, 21, 0, 0),
2153+
GATE(CLK_GOUT_DPU_SSMT_DPU0_PCLK, "gout_dpu_ssmt_dpu0_pclk",
2154+
"dout_dpu_busp",
2155+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK, 21, 0, 0),
2156+
GATE(CLK_GOUT_DPU_SSMT_DPU1_ACLK, "gout_dpu_ssmt_dpu1_aclk",
2157+
"mout_dpu_bus_user",
2158+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK, 21, 0, 0),
2159+
GATE(CLK_GOUT_DPU_SSMT_DPU1_PCLK, "gout_dpu_ssmt_dpu1_pclk",
2160+
"dout_dpu_busp",
2161+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK, 21, 0, 0),
2162+
GATE(CLK_GOUT_DPU_SSMT_DPU2_ACLK, "gout_dpu_ssmt_dpu2_aclk",
2163+
"mout_dpu_bus_user",
2164+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK, 21, 0, 0),
2165+
GATE(CLK_GOUT_DPU_SSMT_DPU2_PCLK, "gout_dpu_ssmt_dpu2_pclk",
2166+
"dout_dpu_busp",
2167+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK, 21, 0, 0),
2168+
GATE(CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S1, "gout_dpu_sysmmu_dpud0_clk_s1",
2169+
"mout_dpu_bus_user",
2170+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1,
2171+
21, 0, 0),
2172+
GATE(CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S2, "gout_dpu_sysmmu_dpud0_clk_s2",
2173+
"mout_dpu_bus_user",
2174+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2,
2175+
21, 0, 0),
2176+
GATE(CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S1, "gout_dpu_sysmmu_dpud1_clk_s1",
2177+
"mout_dpu_bus_user",
2178+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1,
2179+
21, 0, 0),
2180+
GATE(CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S2, "gout_dpu_sysmmu_dpud1_clk_s2",
2181+
"mout_dpu_bus_user",
2182+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2,
2183+
21, 0, 0),
2184+
GATE(CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S1, "gout_dpu_sysmmu_dpud2_clk_s1",
2185+
"mout_dpu_bus_user",
2186+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1,
2187+
21, 0, 0),
2188+
GATE(CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S2, "gout_dpu_sysmmu_dpud2_clk_s2",
2189+
"mout_dpu_bus_user",
2190+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2, 21, 0, 0),
2191+
GATE(CLK_GOUT_DPU_SYSREG_DPU_PCLK, "gout_dpu_sysreg_dpu_pclk",
2192+
"dout_dpu_busp",
2193+
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK, 21, 0, 0),
2194+
};
2195+
2196+
static const struct samsung_cmu_info dpu_cmu_info __initconst = {
2197+
.mux_clks = dpu_mux_clks,
2198+
.nr_mux_clks = ARRAY_SIZE(dpu_mux_clks),
2199+
.div_clks = dpu_div_clks,
2200+
.nr_div_clks = ARRAY_SIZE(dpu_div_clks),
2201+
.gate_clks = dpu_gate_clks,
2202+
.nr_gate_clks = ARRAY_SIZE(dpu_gate_clks),
2203+
.nr_clk_ids = CLKS_NR_DPU,
2204+
.clk_regs = dpu_clk_regs,
2205+
.nr_clk_regs = ARRAY_SIZE(dpu_clk_regs),
2206+
.sysreg_clk_regs = dcrg_memclk_sysreg,
2207+
.nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg),
2208+
.clk_name = "bus",
2209+
.auto_clock_gate = true,
2210+
.gate_dbg_offset = GS101_GATE_DBG_OFFSET,
2211+
.option_offset = DPU_CMU_DPU_CONTROLLER_OPTION,
2212+
.drcg_offset = GS101_DRCG_EN_OFFSET,
2213+
};
2214+
19352215
/* ---- CMU_HSI0 ------------------------------------------------------------ */
19362216

19372217
/* Register Offset definitions for CMU_HSI0 (0x11000000) */
@@ -4443,6 +4723,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
44434723
{
44444724
.compatible = "google,gs101-cmu-apm",
44454725
.data = &apm_cmu_info,
4726+
}, {
4727+
.compatible = "google,gs101-cmu-dpu",
4728+
.data = &dpu_cmu_info,
44464729
}, {
44474730
.compatible = "google,gs101-cmu-hsi0",
44484731
.data = &hsi0_cmu_info,

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