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cristiccvinodkoul
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phy: rockchip: samsung-hdptx: Fix coding style alignment
Handle a bunch of reported checkpatch.pl complaints: CHECK: Alignment should match open parenthesis Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-3-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Lines changed: 6 additions & 6 deletions

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drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1624,11 +1624,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
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regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset,
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LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
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FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
1627-
ctrl->tx_jeq_even_ctrl));
1627+
ctrl->tx_jeq_even_ctrl));
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regmap_update_bits(hdptx->regmap, LANE_REG(030c) + offset,
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LN_TX_JEQ_ODD_CTRL_RBR_MASK,
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FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR_MASK,
1631-
ctrl->tx_jeq_odd_ctrl));
1631+
ctrl->tx_jeq_odd_ctrl));
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regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
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LN_TX_SER_40BIT_EN_RBR_MASK,
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FIELD_PREP(LN_TX_SER_40BIT_EN_RBR_MASK, 0x1));
@@ -1638,11 +1638,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
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regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
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LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
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FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
1641-
ctrl->tx_jeq_even_ctrl));
1641+
ctrl->tx_jeq_even_ctrl));
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regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
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LN_TX_JEQ_ODD_CTRL_HBR_MASK,
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FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR_MASK,
1645-
ctrl->tx_jeq_odd_ctrl));
1645+
ctrl->tx_jeq_odd_ctrl));
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regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
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LN_TX_SER_40BIT_EN_HBR_MASK,
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FIELD_PREP(LN_TX_SER_40BIT_EN_HBR_MASK, 0x1));
@@ -1653,11 +1653,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
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regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
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LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
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FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
1656-
ctrl->tx_jeq_even_ctrl));
1656+
ctrl->tx_jeq_even_ctrl));
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regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
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LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
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FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
1660-
ctrl->tx_jeq_odd_ctrl));
1660+
ctrl->tx_jeq_odd_ctrl));
16611661
regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
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LN_TX_SER_40BIT_EN_HBR2_MASK,
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FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2_MASK, 0x1));

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