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PCI: dwc: Add debugfs based Silicon Debug support for DWC
Add support to provide Silicon Debug interface to userspace. This set of debug registers are part of the RAS DES feature present in DesignWare PCIe controllers. Co-developed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Shradha Todi <shradha.t@samsung.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Fan Ni <fan.ni@samsung.com> Tested-by: Hrishikesh Deleep <hrishikesh.d@samsung.com> Link: https://lore.kernel.org/r/20250221131548.59616-4-shradha.t@samsung.com [kwilczynski: commit log, tidy up Kconfig and drop "default y", tidy up code comments, squashed patch that fixes a NULL pointer dereference when debugfs is already unavailable during clean-up from https://lore.kernel.org/linux-pci/20250225171239.19574-2-manivannan.sadhasivam@linaro.org, refactor dwc_pcie_debugfs_init() to not return errors, squashed patch that changes how lack of the RAS DES capability is handled from https://lore.kernel.org/linux-pci/20250304151814.6xu7cbpwpqrvcad5@thinkpad] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
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‎Documentation/ABI/testing/debugfs-dwc-pcie‎

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@@ -0,0 +1,13 @@
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What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_debug/lane_detect
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Date: February 2025
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Contact: Shradha Todi <shradha.t@samsung.com>
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Description: (RW) Write the lane number to be checked for detection. Read
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will return whether PHY indicates receiver detection on the
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selected lane. The default selected lane is Lane0.
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What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_debug/rx_valid
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Date: February 2025
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Contact: Shradha Todi <shradha.t@samsung.com>
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Description: (RW) Write the lane number to be checked as valid or invalid.
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Read will return the status of PIPE RXVALID signal of the
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selected lane. The default selected lane is Lane0.

‎drivers/pci/controller/dwc/Kconfig‎

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@@ -6,6 +6,16 @@ menu "DesignWare-based PCIe controllers"
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config PCIE_DW
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bool
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config PCIE_DW_DEBUGFS
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bool "DesignWare PCIe debugfs entries"
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depends on DEBUG_FS
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depends on PCIE_DW_HOST || PCIE_DW_EP
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help
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Say Y here to enable debugfs entries for the PCIe controller. These
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entries provide various debug features related to the controller and
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expose the RAS DES capabilities such as Silicon Debug, Error Injection
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and Statistical Counters.
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config PCIE_DW_HOST
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bool
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select PCIE_DW

‎drivers/pci/controller/dwc/Makefile‎

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@@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_PCIE_DW) += pcie-designware.o
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obj-$(CONFIG_PCIE_DW_DEBUGFS) += pcie-designware-debugfs.o
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obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
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obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
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obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o

‎drivers/pci/controller/dwc/pcie-designware-debugfs.c‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Synopsys DesignWare PCIe controller debugfs driver
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*
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* Copyright (C) 2025 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Shradha Todi <shradha.t@samsung.com>
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*/
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#include <linux/debugfs.h>
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#include "pcie-designware.h"
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#define SD_STATUS_L1LANE_REG 0xb0
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#define PIPE_RXVALID BIT(18)
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#define PIPE_DETECT_LANE BIT(17)
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#define LANE_SELECT GENMASK(3, 0)
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#define DWC_DEBUGFS_BUF_MAX 128
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/**
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* struct dwc_pcie_rasdes_info - Stores controller common information
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* @ras_cap_offset: RAS DES vendor specific extended capability offset
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* @reg_event_lock: Mutex used for RAS DES shadow event registers
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*
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* Any parameter constant to all files of the debugfs hierarchy for a single
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* controller will be stored in this struct. It is allocated and assigned to
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* controller specific struct dw_pcie during initialization.
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*/
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struct dwc_pcie_rasdes_info {
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u32 ras_cap_offset;
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struct mutex reg_event_lock;
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};
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static ssize_t lane_detect_read(struct file *file, char __user *buf,
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size_t count, loff_t *ppos)
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{
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struct dw_pcie *pci = file->private_data;
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struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
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char debugfs_buf[DWC_DEBUGFS_BUF_MAX];
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ssize_t pos;
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u32 val;
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val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG);
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val = FIELD_GET(PIPE_DETECT_LANE, val);
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if (val)
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pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Lane Detected\n");
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else
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pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Lane Undetected\n");
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return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
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}
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static ssize_t lane_detect_write(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos)
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{
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struct dw_pcie *pci = file->private_data;
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struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
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u32 lane, val;
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val = kstrtou32_from_user(buf, count, 0, &lane);
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if (val)
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return val;
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val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG);
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val &= ~(LANE_SELECT);
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val |= FIELD_PREP(LANE_SELECT, lane);
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dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG, val);
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return count;
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}
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static ssize_t rx_valid_read(struct file *file, char __user *buf,
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size_t count, loff_t *ppos)
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{
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struct dw_pcie *pci = file->private_data;
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struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
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char debugfs_buf[DWC_DEBUGFS_BUF_MAX];
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ssize_t pos;
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u32 val;
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val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG);
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val = FIELD_GET(PIPE_RXVALID, val);
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if (val)
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pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "RX Valid\n");
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else
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pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "RX Invalid\n");
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return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
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}
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static ssize_t rx_valid_write(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos)
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{
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return lane_detect_write(file, buf, count, ppos);
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}
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#define dwc_debugfs_create(name) \
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debugfs_create_file(#name, 0644, rasdes_debug, pci, \
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&dbg_ ## name ## _fops)
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#define DWC_DEBUGFS_FOPS(name) \
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static const struct file_operations dbg_ ## name ## _fops = { \
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.open = simple_open, \
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.read = name ## _read, \
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.write = name ## _write \
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}
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DWC_DEBUGFS_FOPS(lane_detect);
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DWC_DEBUGFS_FOPS(rx_valid);
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static void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci)
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{
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struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
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mutex_destroy(&rinfo->reg_event_lock);
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}
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static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir)
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{
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struct dentry *rasdes_debug;
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struct dwc_pcie_rasdes_info *rasdes_info;
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struct device *dev = pci->dev;
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int ras_cap;
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/*
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* If a given SoC has no RAS DES capability, the following call is
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* bound to return an error, breaking some existing platforms. So,
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* return 0 here, as this is not necessarily an error.
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*/
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ras_cap = dw_pcie_find_rasdes_capability(pci);
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if (!ras_cap) {
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dev_dbg(dev, "no RAS DES capability available\n");
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return 0;
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}
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rasdes_info = devm_kzalloc(dev, sizeof(*rasdes_info), GFP_KERNEL);
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if (!rasdes_info)
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return -ENOMEM;
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/* Create subdirectories for Debug, Error Injection, Statistics. */
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rasdes_debug = debugfs_create_dir("rasdes_debug", dir);
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mutex_init(&rasdes_info->reg_event_lock);
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rasdes_info->ras_cap_offset = ras_cap;
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pci->debugfs->rasdes_info = rasdes_info;
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/* Create debugfs files for Debug subdirectory. */
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dwc_debugfs_create(lane_detect);
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dwc_debugfs_create(rx_valid);
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return 0;
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}
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void dwc_pcie_debugfs_deinit(struct dw_pcie *pci)
157+
{
158+
if (!pci->debugfs)
159+
return;
160+
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dwc_pcie_rasdes_debugfs_deinit(pci);
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debugfs_remove_recursive(pci->debugfs->debug_dir);
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}
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void dwc_pcie_debugfs_init(struct dw_pcie *pci)
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{
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char dirname[DWC_DEBUGFS_BUF_MAX];
168+
struct device *dev = pci->dev;
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struct debugfs_info *debugfs;
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struct dentry *dir;
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int err;
172+
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/* Create main directory for each platform driver. */
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snprintf(dirname, DWC_DEBUGFS_BUF_MAX, "dwc_pcie_%s", dev_name(dev));
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dir = debugfs_create_dir(dirname, NULL);
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debugfs = devm_kzalloc(dev, sizeof(*debugfs), GFP_KERNEL);
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if (!debugfs)
178+
return;
179+
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debugfs->debug_dir = dir;
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pci->debugfs = debugfs;
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err = dwc_pcie_rasdes_debugfs_init(pci, dir);
183+
if (err)
184+
dev_err(dev, "failed to initialize RAS DES debugfs, err=%d\n",
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err);
186+
}

‎drivers/pci/controller/dwc/pcie-designware-ep.c‎

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@@ -666,6 +666,7 @@ void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep)
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{
667667
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
668668

669+
dwc_pcie_debugfs_deinit(pci);
669670
dw_pcie_edma_remove(pci);
670671
}
671672
EXPORT_SYMBOL_GPL(dw_pcie_ep_cleanup);
@@ -837,6 +838,8 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep)
837838

838839
dw_pcie_ep_init_non_sticky_registers(pci);
839840

841+
dwc_pcie_debugfs_init(pci);
842+
840843
return 0;
841844

842845
err_remove_edma:

‎drivers/pci/controller/dwc/pcie-designware-host.c‎

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@@ -548,6 +548,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
548548
if (pp->ops->post_init)
549549
pp->ops->post_init(pp);
550550

551+
dwc_pcie_debugfs_init(pci);
552+
551553
return 0;
552554

553555
err_stop_link:
@@ -572,6 +574,8 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
572574
{
573575
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
574576

577+
dwc_pcie_debugfs_deinit(pci);
578+
575579
pci_stop_root_bus(pp->bridge->bus);
576580
pci_remove_root_bus(pp->bridge->bus);
577581

‎drivers/pci/controller/dwc/pcie-designware.c‎

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@@ -323,6 +323,12 @@ static u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci,
323323
return 0;
324324
}
325325

326+
u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci)
327+
{
328+
return dw_pcie_find_vsec_capability(pci, dwc_pcie_rasdes_vsec_ids);
329+
}
330+
EXPORT_SYMBOL_GPL(dw_pcie_find_rasdes_capability);
331+
326332
int dw_pcie_read(void __iomem *addr, int size, u32 *val)
327333
{
328334
if (!IS_ALIGNED((uintptr_t)addr, size)) {

‎drivers/pci/controller/dwc/pcie-designware.h‎

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@@ -437,6 +437,11 @@ struct dw_pcie_ops {
437437
void (*stop_link)(struct dw_pcie *pcie);
438438
};
439439

440+
struct debugfs_info {
441+
struct dentry *debug_dir;
442+
void *rasdes_info;
443+
};
444+
440445
struct dw_pcie {
441446
struct device *dev;
442447
void __iomem *dbi_base;
@@ -465,6 +470,7 @@ struct dw_pcie {
465470
struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS];
466471
struct gpio_desc *pe_rst;
467472
bool suspended;
473+
struct debugfs_info *debugfs;
468474
};
469475

470476
#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
@@ -478,6 +484,7 @@ void dw_pcie_version_detect(struct dw_pcie *pci);
478484

479485
u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
480486
u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap);
487+
u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci);
481488

482489
int dw_pcie_read(void __iomem *addr, int size, u32 *val);
483490
int dw_pcie_write(void __iomem *addr, int size, u32 val);
@@ -806,4 +813,17 @@ dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no)
806813
return NULL;
807814
}
808815
#endif
816+
817+
#ifdef CONFIG_PCIE_DW_DEBUGFS
818+
void dwc_pcie_debugfs_init(struct dw_pcie *pci);
819+
void dwc_pcie_debugfs_deinit(struct dw_pcie *pci);
820+
#else
821+
static inline void dwc_pcie_debugfs_init(struct dw_pcie *pci)
822+
{
823+
}
824+
static inline void dwc_pcie_debugfs_deinit(struct dw_pcie *pci)
825+
{
826+
}
827+
#endif
828+
809829
#endif /* _PCIE_DESIGNWARE_H */

‎include/linux/pcie-dwc.h‎

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@@ -28,6 +28,8 @@ static const struct dwc_pcie_vsec_id dwc_pcie_rasdes_vsec_ids[] = {
2828
.vsec_id = 0x02, .vsec_rev = 0x4 },
2929
{ .vendor_id = PCI_VENDOR_ID_QCOM,
3030
.vsec_id = 0x02, .vsec_rev = 0x4 },
31+
{ .vendor_id = PCI_VENDOR_ID_SAMSUNG,
32+
.vsec_id = 0x02, .vsec_rev = 0x4 },
3133
{}
3234
};
3335

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