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anderssonandersson
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Merge branch '20230223180935.60546-1-otto.pflueger@abscue.de' into clk-for-6.4
Merge MSM8917 Global Clock Controller and RPM clock controller bindings through topic branch, to make it possible to introduce in Devicetree source depending on these.
2 parents fe084c6 + 9408225 commit 518634f

3 files changed

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‎Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml‎

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$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on MSM8909
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title: Qualcomm Global Clock & Reset Controller on MSM8909, MSM8917 and QM215
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maintainers:
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- Stephan Gerhold <stephan@gerhold.net>
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description: |
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Qualcomm global clock control module provides the clocks, resets and power
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domains on MSM8909.
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domains on MSM8909, MSM8917 or QM215.
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See also:: include/dt-bindings/clock/qcom,gcc-msm8909.h
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See also::
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include/dt-bindings/clock/qcom,gcc-msm8909.h
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include/dt-bindings/clock/qcom,gcc-msm8917.h
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properties:
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compatible:
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const: qcom,gcc-msm8909
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enum:
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- qcom,gcc-msm8909
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- qcom,gcc-msm8917
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- qcom,gcc-qm215
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clocks:
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items:

‎Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml‎

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- qcom,rpmcc-msm8660
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- qcom,rpmcc-msm8909
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- qcom,rpmcc-msm8916
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- qcom,rpmcc-msm8917
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- qcom,rpmcc-msm8936
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- qcom,rpmcc-msm8953
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- qcom,rpmcc-msm8974
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- qcom,rpmcc-mdm9607
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- qcom,rpmcc-msm8226
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- qcom,rpmcc-msm8916
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- qcom,rpmcc-msm8917
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- qcom,rpmcc-msm8936
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- qcom,rpmcc-msm8953
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- qcom,rpmcc-msm8974

‎include/dt-bindings/clock/qcom,gcc-msm8917.h‎

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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#ifndef _DT_BINDINGS_CLK_MSM_GCC_8917_H
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#define _DT_BINDINGS_CLK_MSM_GCC_8917_H
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/* Clocks */
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#define APSS_AHB_CLK_SRC 0
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 1
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 2
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 3
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 4
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 5
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 6
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#define BLSP1_UART1_APPS_CLK_SRC 7
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#define BLSP1_UART2_APPS_CLK_SRC 8
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#define BLSP2_QUP1_I2C_APPS_CLK_SRC 9
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#define BLSP2_QUP1_SPI_APPS_CLK_SRC 10
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#define BLSP2_QUP2_I2C_APPS_CLK_SRC 11
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#define BLSP2_QUP2_SPI_APPS_CLK_SRC 12
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#define BLSP2_QUP3_I2C_APPS_CLK_SRC 13
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#define BLSP2_QUP3_SPI_APPS_CLK_SRC 14
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#define BLSP2_UART1_APPS_CLK_SRC 15
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#define BLSP2_UART2_APPS_CLK_SRC 16
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#define BYTE0_CLK_SRC 17
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#define CAMSS_GP0_CLK_SRC 18
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#define CAMSS_GP1_CLK_SRC 19
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#define CAMSS_TOP_AHB_CLK_SRC 20
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#define CCI_CLK_SRC 21
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#define CPP_CLK_SRC 22
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#define CRYPTO_CLK_SRC 23
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#define CSI0PHYTIMER_CLK_SRC 24
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#define CSI0_CLK_SRC 25
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#define CSI1PHYTIMER_CLK_SRC 26
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#define CSI1_CLK_SRC 27
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#define CSI2_CLK_SRC 28
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#define ESC0_CLK_SRC 29
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#define GCC_APSS_TCU_CLK 30
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#define GCC_BIMC_GFX_CLK 31
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#define GCC_BIMC_GPU_CLK 32
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#define GCC_BLSP1_AHB_CLK 33
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 34
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 35
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 36
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 37
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 38
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 39
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#define GCC_BLSP1_UART1_APPS_CLK 40
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#define GCC_BLSP1_UART2_APPS_CLK 41
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#define GCC_BLSP2_AHB_CLK 42
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#define GCC_BLSP2_QUP1_I2C_APPS_CLK 43
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#define GCC_BLSP2_QUP1_SPI_APPS_CLK 44
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#define GCC_BLSP2_QUP2_I2C_APPS_CLK 45
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#define GCC_BLSP2_QUP2_SPI_APPS_CLK 46
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#define GCC_BLSP2_QUP3_I2C_APPS_CLK 47
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#define GCC_BLSP2_QUP3_SPI_APPS_CLK 48
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#define GCC_BLSP2_UART1_APPS_CLK 49
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#define GCC_BLSP2_UART2_APPS_CLK 50
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#define GCC_BOOT_ROM_AHB_CLK 51
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#define GCC_CAMSS_AHB_CLK 52
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#define GCC_CAMSS_CCI_AHB_CLK 53
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#define GCC_CAMSS_CCI_CLK 54
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#define GCC_CAMSS_CPP_AHB_CLK 55
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#define GCC_CAMSS_CPP_CLK 56
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#define GCC_CAMSS_CSI0PHYTIMER_CLK 57
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#define GCC_CAMSS_CSI0PHY_CLK 58
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#define GCC_CAMSS_CSI0PIX_CLK 59
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#define GCC_CAMSS_CSI0RDI_CLK 60
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#define GCC_CAMSS_CSI0_AHB_CLK 61
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#define GCC_CAMSS_CSI0_CLK 62
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#define GCC_CAMSS_CSI1PHYTIMER_CLK 63
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#define GCC_CAMSS_CSI1PHY_CLK 64
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#define GCC_CAMSS_CSI1PIX_CLK 65
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#define GCC_CAMSS_CSI1RDI_CLK 66
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#define GCC_CAMSS_CSI1_AHB_CLK 67
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#define GCC_CAMSS_CSI1_CLK 68
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#define GCC_CAMSS_CSI2PHY_CLK 69
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#define GCC_CAMSS_CSI2PIX_CLK 70
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#define GCC_CAMSS_CSI2RDI_CLK 71
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#define GCC_CAMSS_CSI2_AHB_CLK 72
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#define GCC_CAMSS_CSI2_CLK 73
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#define GCC_CAMSS_CSI_VFE0_CLK 74
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#define GCC_CAMSS_CSI_VFE1_CLK 75
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#define GCC_CAMSS_GP0_CLK 76
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#define GCC_CAMSS_GP1_CLK 77
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#define GCC_CAMSS_ISPIF_AHB_CLK 78
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#define GCC_CAMSS_JPEG0_CLK 79
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#define GCC_CAMSS_JPEG_AHB_CLK 80
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#define GCC_CAMSS_JPEG_AXI_CLK 81
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#define GCC_CAMSS_MCLK0_CLK 82
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#define GCC_CAMSS_MCLK1_CLK 83
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#define GCC_CAMSS_MCLK2_CLK 84
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#define GCC_CAMSS_MICRO_AHB_CLK 85
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#define GCC_CAMSS_TOP_AHB_CLK 86
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#define GCC_CAMSS_VFE0_AHB_CLK 87
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#define GCC_CAMSS_VFE0_AXI_CLK 88
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#define GCC_CAMSS_VFE0_CLK 89
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#define GCC_CAMSS_VFE1_AHB_CLK 90
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#define GCC_CAMSS_VFE1_AXI_CLK 91
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#define GCC_CAMSS_VFE1_CLK 92
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#define GCC_CPP_TBU_CLK 93
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#define GCC_CRYPTO_AHB_CLK 94
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#define GCC_CRYPTO_AXI_CLK 95
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#define GCC_CRYPTO_CLK 96
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#define GCC_DCC_CLK 97
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#define GCC_GFX_TBU_CLK 98
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#define GCC_GFX_TCU_CLK 99
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#define GCC_GP1_CLK 100
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#define GCC_GP2_CLK 101
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#define GCC_GP3_CLK 102
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#define GCC_GTCU_AHB_CLK 103
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#define GCC_JPEG_TBU_CLK 104
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#define GCC_MDP_TBU_CLK 105
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#define GCC_MDSS_AHB_CLK 106
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#define GCC_MDSS_AXI_CLK 107
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#define GCC_MDSS_BYTE0_CLK 108
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#define GCC_MDSS_ESC0_CLK 109
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#define GCC_MDSS_MDP_CLK 110
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#define GCC_MDSS_PCLK0_CLK 111
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#define GCC_MDSS_VSYNC_CLK 112
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#define GCC_MSS_CFG_AHB_CLK 113
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#define GCC_MSS_Q6_BIMC_AXI_CLK 114
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#define GCC_OXILI_AHB_CLK 115
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#define GCC_OXILI_GFX3D_CLK 116
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#define GCC_PDM2_CLK 117
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#define GCC_PDM_AHB_CLK 118
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#define GCC_PRNG_AHB_CLK 119
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#define GCC_QDSS_DAP_CLK 120
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#define GCC_SDCC1_AHB_CLK 121
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#define GCC_SDCC1_APPS_CLK 122
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#define GCC_SDCC1_ICE_CORE_CLK 123
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#define GCC_SDCC2_AHB_CLK 124
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#define GCC_SDCC2_APPS_CLK 125
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#define GCC_SMMU_CFG_CLK 126
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#define GCC_USB2A_PHY_SLEEP_CLK 127
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#define GCC_USB_HS_AHB_CLK 128
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#define GCC_USB_HS_PHY_CFG_AHB_CLK 129
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#define GCC_USB_HS_SYSTEM_CLK 130
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#define GCC_VENUS0_AHB_CLK 131
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#define GCC_VENUS0_AXI_CLK 132
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#define GCC_VENUS0_CORE0_VCODEC0_CLK 133
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#define GCC_VENUS0_VCODEC0_CLK 134
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#define GCC_VENUS_TBU_CLK 135
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#define GCC_VFE1_TBU_CLK 136
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#define GCC_VFE_TBU_CLK 137
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#define GFX3D_CLK_SRC 138
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#define GP1_CLK_SRC 139
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#define GP2_CLK_SRC 140
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#define GP3_CLK_SRC 141
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#define GPLL0 142
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#define GPLL0_EARLY 143
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#define GPLL3 144
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#define GPLL3_EARLY 145
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#define GPLL4 146
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#define GPLL4_EARLY 147
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#define GPLL6 148
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#define GPLL6_EARLY 149
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#define JPEG0_CLK_SRC 150
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#define MCLK0_CLK_SRC 151
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#define MCLK1_CLK_SRC 152
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#define MCLK2_CLK_SRC 153
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#define MDP_CLK_SRC 154
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#define PCLK0_CLK_SRC 155
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#define PDM2_CLK_SRC 156
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#define SDCC1_APPS_CLK_SRC 157
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#define SDCC1_ICE_CORE_CLK_SRC 158
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#define SDCC2_APPS_CLK_SRC 159
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#define USB_HS_SYSTEM_CLK_SRC 160
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#define VCODEC0_CLK_SRC 161
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#define VFE0_CLK_SRC 162
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#define VFE1_CLK_SRC 163
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#define VSYNC_CLK_SRC 164
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/* GCC block resets */
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#define GCC_CAMSS_MICRO_BCR 0
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#define GCC_MSS_BCR 1
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#define GCC_QUSB2_PHY_BCR 2
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#define GCC_USB_HS_BCR 3
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#define GCC_USB2_HS_PHY_ONLY_BCR 4
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/* GDSCs */
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#define CPP_GDSC 0
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#define JPEG_GDSC 1
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#define MDSS_GDSC 2
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#define OXILI_GX_GDSC 3
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#define VENUS_CORE0_GDSC 4
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#define VENUS_GDSC 5
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#define VFE0_GDSC 6
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#define VFE1_GDSC 7
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#endif

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