Skip to content

Commit 51fc01a

Browse files
superna9999superna9999
committed
drm/meson: venc: add ENCL encoder setup for MIPI-DSI output
This adds supports for the ENCL encoder connected to a MIPI-DSI transceiver on the Amlogic AXG, G12A, G12B & SM1 SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Nicolas Belin <nbelin@baylibre.com> Tested-by: Nicolas Belin <nbelin@baylibre.com> # on Khadas VIM3 + TS050 Panel Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-10-56eb7a4d5b8e@linaro.org
1 parent 44e1616 commit 51fc01a

4 files changed

Lines changed: 242 additions & 2 deletions

File tree

‎drivers/gpu/drm/meson/meson_registers.h‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -812,6 +812,7 @@
812812
#define VENC_STATA 0x1b6d
813813
#define VENC_INTCTRL 0x1b6e
814814
#define VENC_INTCTRL_ENCI_LNRST_INT_EN BIT(1)
815+
#define VENC_INTCTRL_ENCP_LNRST_INT_EN BIT(9)
815816
#define VENC_INTFLAG 0x1b6f
816817
#define VENC_VIDEO_TST_EN 0x1b70
817818
#define VENC_VIDEO_TST_MDSEL 0x1b71
@@ -1192,7 +1193,11 @@
11921193
#define ENCL_VIDEO_PB_OFFST 0x1ca5
11931194
#define ENCL_VIDEO_PR_OFFST 0x1ca6
11941195
#define ENCL_VIDEO_MODE 0x1ca7
1196+
#define ENCL_PX_LN_CNT_SHADOW_EN BIT(15)
11951197
#define ENCL_VIDEO_MODE_ADV 0x1ca8
1198+
#define ENCL_VIDEO_MODE_ADV_VFIFO_EN BIT(3)
1199+
#define ENCL_VIDEO_MODE_ADV_GAIN_HDTV BIT(4)
1200+
#define ENCL_SEL_GAMMA_RGB_IN BIT(10)
11961201
#define ENCL_DBG_PX_RST 0x1ca9
11971202
#define ENCL_DBG_LN_RST 0x1caa
11981203
#define ENCL_DBG_PX_INT 0x1cab
@@ -1219,11 +1224,14 @@
12191224
#define ENCL_VIDEO_VOFFST 0x1cc0
12201225
#define ENCL_VIDEO_RGB_CTRL 0x1cc1
12211226
#define ENCL_VIDEO_FILT_CTRL 0x1cc2
1227+
#define ENCL_VIDEO_FILT_CTRL_BYPASS_FILTER BIT(12)
12221228
#define ENCL_VIDEO_OFLD_VPEQ_OFST 0x1cc3
12231229
#define ENCL_VIDEO_OFLD_VOAV_OFST 0x1cc4
12241230
#define ENCL_VIDEO_MATRIX_CB 0x1cc5
12251231
#define ENCL_VIDEO_MATRIX_CR 0x1cc6
12261232
#define ENCL_VIDEO_RGBIN_CTRL 0x1cc7
1233+
#define ENCL_VIDEO_RGBIN_RGB BIT(0)
1234+
#define ENCL_VIDEO_RGBIN_ZBLK BIT(1)
12271235
#define ENCL_MAX_LINE_SWITCH_POINT 0x1cc8
12281236
#define ENCL_DACSEL_0 0x1cc9
12291237
#define ENCL_DACSEL_1 0x1cca
@@ -1300,13 +1308,28 @@
13001308
#define RDMA_STATUS2 0x1116
13011309
#define RDMA_STATUS3 0x1117
13021310
#define L_GAMMA_CNTL_PORT 0x1400
1311+
#define L_GAMMA_CNTL_PORT_VCOM_POL BIT(7) /* RW */
1312+
#define L_GAMMA_CNTL_PORT_RVS_OUT BIT(6) /* RW */
1313+
#define L_GAMMA_CNTL_PORT_ADR_RDY BIT(5) /* Read Only */
1314+
#define L_GAMMA_CNTL_PORT_WR_RDY BIT(4) /* Read Only */
1315+
#define L_GAMMA_CNTL_PORT_RD_RDY BIT(3) /* Read Only */
1316+
#define L_GAMMA_CNTL_PORT_TR BIT(2) /* RW */
1317+
#define L_GAMMA_CNTL_PORT_SET BIT(1) /* RW */
1318+
#define L_GAMMA_CNTL_PORT_EN BIT(0) /* RW */
13031319
#define L_GAMMA_DATA_PORT 0x1401
13041320
#define L_GAMMA_ADDR_PORT 0x1402
1321+
#define L_GAMMA_ADDR_PORT_RD BIT(12)
1322+
#define L_GAMMA_ADDR_PORT_AUTO_INC BIT(11)
1323+
#define L_GAMMA_ADDR_PORT_SEL_R BIT(10)
1324+
#define L_GAMMA_ADDR_PORT_SEL_G BIT(9)
1325+
#define L_GAMMA_ADDR_PORT_SEL_B BIT(8)
1326+
#define L_GAMMA_ADDR_PORT_ADDR GENMASK(7, 0)
13051327
#define L_GAMMA_VCOM_HSWITCH_ADDR 0x1403
13061328
#define L_RGB_BASE_ADDR 0x1405
13071329
#define L_RGB_COEFF_ADDR 0x1406
13081330
#define L_POL_CNTL_ADDR 0x1407
13091331
#define L_DITH_CNTL_ADDR 0x1408
1332+
#define L_DITH_CNTL_DITH10_EN BIT(10)
13101333
#define L_GAMMA_PROBE_CTRL 0x1409
13111334
#define L_GAMMA_PROBE_COLOR_L 0x140a
13121335
#define L_GAMMA_PROBE_COLOR_H 0x140b
@@ -1363,6 +1386,8 @@
13631386
#define L_LCD_PWM1_HI_ADDR 0x143f
13641387
#define L_INV_CNT_ADDR 0x1440
13651388
#define L_TCON_MISC_SEL_ADDR 0x1441
1389+
#define L_TCON_MISC_SEL_STV1 BIT(4)
1390+
#define L_TCON_MISC_SEL_STV2 BIT(5)
13661391
#define L_DUAL_PORT_CNTL_ADDR 0x1442
13671392
#define MLVDS_CLK_CTL1_HI 0x1443
13681393
#define MLVDS_CLK_CTL1_LO 0x1444

‎drivers/gpu/drm/meson/meson_venc.c‎

Lines changed: 209 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
*/
77

88
#include <linux/export.h>
9+
#include <linux/iopoll.h>
910

1011
#include <drm/drm_modes.h>
1112

@@ -1557,6 +1558,205 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
15571558
}
15581559
EXPORT_SYMBOL_GPL(meson_venc_hdmi_mode_set);
15591560

1561+
static unsigned short meson_encl_gamma_table[256] = {
1562+
0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60,
1563+
64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124,
1564+
128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 180, 184, 188,
1565+
192, 196, 200, 204, 208, 212, 216, 220, 224, 228, 232, 236, 240, 244, 248, 252,
1566+
256, 260, 264, 268, 272, 276, 280, 284, 288, 292, 296, 300, 304, 308, 312, 316,
1567+
320, 324, 328, 332, 336, 340, 344, 348, 352, 356, 360, 364, 368, 372, 376, 380,
1568+
384, 388, 392, 396, 400, 404, 408, 412, 416, 420, 424, 428, 432, 436, 440, 444,
1569+
448, 452, 456, 460, 464, 468, 472, 476, 480, 484, 488, 492, 496, 500, 504, 508,
1570+
512, 516, 520, 524, 528, 532, 536, 540, 544, 548, 552, 556, 560, 564, 568, 572,
1571+
576, 580, 584, 588, 592, 596, 600, 604, 608, 612, 616, 620, 624, 628, 632, 636,
1572+
640, 644, 648, 652, 656, 660, 664, 668, 672, 676, 680, 684, 688, 692, 696, 700,
1573+
704, 708, 712, 716, 720, 724, 728, 732, 736, 740, 744, 748, 752, 756, 760, 764,
1574+
768, 772, 776, 780, 784, 788, 792, 796, 800, 804, 808, 812, 816, 820, 824, 828,
1575+
832, 836, 840, 844, 848, 852, 856, 860, 864, 868, 872, 876, 880, 884, 888, 892,
1576+
896, 900, 904, 908, 912, 916, 920, 924, 928, 932, 936, 940, 944, 948, 952, 956,
1577+
960, 964, 968, 972, 976, 980, 984, 988, 992, 996, 1000, 1004, 1008, 1012, 1016, 1020,
1578+
};
1579+
1580+
static void meson_encl_set_gamma_table(struct meson_drm *priv, u16 *data,
1581+
u32 rgb_mask)
1582+
{
1583+
int i, ret;
1584+
u32 reg;
1585+
1586+
writel_bits_relaxed(L_GAMMA_CNTL_PORT_EN, 0,
1587+
priv->io_base + _REG(L_GAMMA_CNTL_PORT));
1588+
1589+
ret = readl_relaxed_poll_timeout(priv->io_base + _REG(L_GAMMA_CNTL_PORT),
1590+
reg, reg & L_GAMMA_CNTL_PORT_ADR_RDY, 10, 10000);
1591+
if (ret)
1592+
pr_warn("%s: GAMMA ADR_RDY timeout\n", __func__);
1593+
1594+
writel_relaxed(L_GAMMA_ADDR_PORT_AUTO_INC | rgb_mask |
1595+
FIELD_PREP(L_GAMMA_ADDR_PORT_ADDR, 0),
1596+
priv->io_base + _REG(L_GAMMA_ADDR_PORT));
1597+
1598+
for (i = 0; i < 256; i++) {
1599+
ret = readl_relaxed_poll_timeout(priv->io_base + _REG(L_GAMMA_CNTL_PORT),
1600+
reg, reg & L_GAMMA_CNTL_PORT_WR_RDY,
1601+
10, 10000);
1602+
if (ret)
1603+
pr_warn_once("%s: GAMMA WR_RDY timeout\n", __func__);
1604+
1605+
writel_relaxed(data[i], priv->io_base + _REG(L_GAMMA_DATA_PORT));
1606+
}
1607+
1608+
ret = readl_relaxed_poll_timeout(priv->io_base + _REG(L_GAMMA_CNTL_PORT),
1609+
reg, reg & L_GAMMA_CNTL_PORT_ADR_RDY, 10, 10000);
1610+
if (ret)
1611+
pr_warn("%s: GAMMA ADR_RDY timeout\n", __func__);
1612+
1613+
writel_relaxed(L_GAMMA_ADDR_PORT_AUTO_INC | rgb_mask |
1614+
FIELD_PREP(L_GAMMA_ADDR_PORT_ADDR, 0x23),
1615+
priv->io_base + _REG(L_GAMMA_ADDR_PORT));
1616+
}
1617+
1618+
void meson_encl_load_gamma(struct meson_drm *priv)
1619+
{
1620+
meson_encl_set_gamma_table(priv, meson_encl_gamma_table, L_GAMMA_ADDR_PORT_SEL_R);
1621+
meson_encl_set_gamma_table(priv, meson_encl_gamma_table, L_GAMMA_ADDR_PORT_SEL_G);
1622+
meson_encl_set_gamma_table(priv, meson_encl_gamma_table, L_GAMMA_ADDR_PORT_SEL_B);
1623+
1624+
writel_bits_relaxed(L_GAMMA_CNTL_PORT_EN, L_GAMMA_CNTL_PORT_EN,
1625+
priv->io_base + _REG(L_GAMMA_CNTL_PORT));
1626+
}
1627+
1628+
void meson_venc_mipi_dsi_mode_set(struct meson_drm *priv,
1629+
const struct drm_display_mode *mode)
1630+
{
1631+
unsigned int max_pxcnt;
1632+
unsigned int max_lncnt;
1633+
unsigned int havon_begin;
1634+
unsigned int havon_end;
1635+
unsigned int vavon_bline;
1636+
unsigned int vavon_eline;
1637+
unsigned int hso_begin;
1638+
unsigned int hso_end;
1639+
unsigned int vso_begin;
1640+
unsigned int vso_end;
1641+
unsigned int vso_bline;
1642+
unsigned int vso_eline;
1643+
1644+
max_pxcnt = mode->htotal - 1;
1645+
max_lncnt = mode->vtotal - 1;
1646+
havon_begin = mode->htotal - mode->hsync_start;
1647+
havon_end = havon_begin + mode->hdisplay - 1;
1648+
vavon_bline = mode->vtotal - mode->vsync_start;
1649+
vavon_eline = vavon_bline + mode->vdisplay - 1;
1650+
hso_begin = 0;
1651+
hso_end = mode->hsync_end - mode->hsync_start;
1652+
vso_begin = 0;
1653+
vso_end = 0;
1654+
vso_bline = 0;
1655+
vso_eline = mode->vsync_end - mode->vsync_start;
1656+
1657+
meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCL);
1658+
1659+
writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
1660+
1661+
writel_relaxed(ENCL_PX_LN_CNT_SHADOW_EN, priv->io_base + _REG(ENCL_VIDEO_MODE));
1662+
writel_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN |
1663+
ENCL_VIDEO_MODE_ADV_GAIN_HDTV |
1664+
ENCL_SEL_GAMMA_RGB_IN, priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
1665+
1666+
writel_relaxed(ENCL_VIDEO_FILT_CTRL_BYPASS_FILTER,
1667+
priv->io_base + _REG(ENCL_VIDEO_FILT_CTRL));
1668+
writel_relaxed(max_pxcnt, priv->io_base + _REG(ENCL_VIDEO_MAX_PXCNT));
1669+
writel_relaxed(max_lncnt, priv->io_base + _REG(ENCL_VIDEO_MAX_LNCNT));
1670+
writel_relaxed(havon_begin, priv->io_base + _REG(ENCL_VIDEO_HAVON_BEGIN));
1671+
writel_relaxed(havon_end, priv->io_base + _REG(ENCL_VIDEO_HAVON_END));
1672+
writel_relaxed(vavon_bline, priv->io_base + _REG(ENCL_VIDEO_VAVON_BLINE));
1673+
writel_relaxed(vavon_eline, priv->io_base + _REG(ENCL_VIDEO_VAVON_ELINE));
1674+
1675+
writel_relaxed(hso_begin, priv->io_base + _REG(ENCL_VIDEO_HSO_BEGIN));
1676+
writel_relaxed(hso_end, priv->io_base + _REG(ENCL_VIDEO_HSO_END));
1677+
writel_relaxed(vso_begin, priv->io_base + _REG(ENCL_VIDEO_VSO_BEGIN));
1678+
writel_relaxed(vso_end, priv->io_base + _REG(ENCL_VIDEO_VSO_END));
1679+
writel_relaxed(vso_bline, priv->io_base + _REG(ENCL_VIDEO_VSO_BLINE));
1680+
writel_relaxed(vso_eline, priv->io_base + _REG(ENCL_VIDEO_VSO_ELINE));
1681+
writel_relaxed(ENCL_VIDEO_RGBIN_RGB | ENCL_VIDEO_RGBIN_ZBLK,
1682+
priv->io_base + _REG(ENCL_VIDEO_RGBIN_CTRL));
1683+
1684+
/* default black pattern */
1685+
writel_relaxed(0, priv->io_base + _REG(ENCL_TST_MDSEL));
1686+
writel_relaxed(0, priv->io_base + _REG(ENCL_TST_Y));
1687+
writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CB));
1688+
writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CR));
1689+
writel_relaxed(1, priv->io_base + _REG(ENCL_TST_EN));
1690+
writel_bits_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN, 0,
1691+
priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
1692+
1693+
writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN));
1694+
1695+
writel_relaxed(0, priv->io_base + _REG(L_RGB_BASE_ADDR));
1696+
writel_relaxed(0x400, priv->io_base + _REG(L_RGB_COEFF_ADDR)); /* Magic value */
1697+
1698+
writel_relaxed(L_DITH_CNTL_DITH10_EN, priv->io_base + _REG(L_DITH_CNTL_ADDR));
1699+
1700+
/* DE signal for TTL */
1701+
writel_relaxed(havon_begin, priv->io_base + _REG(L_OEH_HS_ADDR));
1702+
writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEH_HE_ADDR));
1703+
writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEH_VS_ADDR));
1704+
writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEH_VE_ADDR));
1705+
1706+
/* DE signal for TTL */
1707+
writel_relaxed(havon_begin, priv->io_base + _REG(L_OEV1_HS_ADDR));
1708+
writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEV1_HE_ADDR));
1709+
writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEV1_VS_ADDR));
1710+
writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEV1_VE_ADDR));
1711+
1712+
/* Hsync signal for TTL */
1713+
if (mode->flags & DRM_MODE_FLAG_PHSYNC) {
1714+
writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HS_ADDR));
1715+
writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HE_ADDR));
1716+
} else {
1717+
writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HS_ADDR));
1718+
writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HE_ADDR));
1719+
}
1720+
writel_relaxed(0, priv->io_base + _REG(L_STH1_VS_ADDR));
1721+
writel_relaxed(max_lncnt, priv->io_base + _REG(L_STH1_VE_ADDR));
1722+
1723+
/* Vsync signal for TTL */
1724+
writel_relaxed(vso_begin, priv->io_base + _REG(L_STV1_HS_ADDR));
1725+
writel_relaxed(vso_end, priv->io_base + _REG(L_STV1_HE_ADDR));
1726+
if (mode->flags & DRM_MODE_FLAG_PVSYNC) {
1727+
writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VS_ADDR));
1728+
writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VE_ADDR));
1729+
} else {
1730+
writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VS_ADDR));
1731+
writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VE_ADDR));
1732+
}
1733+
1734+
/* DE signal */
1735+
writel_relaxed(havon_begin, priv->io_base + _REG(L_DE_HS_ADDR));
1736+
writel_relaxed(havon_end + 1, priv->io_base + _REG(L_DE_HE_ADDR));
1737+
writel_relaxed(vavon_bline, priv->io_base + _REG(L_DE_VS_ADDR));
1738+
writel_relaxed(vavon_eline, priv->io_base + _REG(L_DE_VE_ADDR));
1739+
1740+
/* Hsync signal */
1741+
writel_relaxed(hso_begin, priv->io_base + _REG(L_HSYNC_HS_ADDR));
1742+
writel_relaxed(hso_end, priv->io_base + _REG(L_HSYNC_HE_ADDR));
1743+
writel_relaxed(0, priv->io_base + _REG(L_HSYNC_VS_ADDR));
1744+
writel_relaxed(max_lncnt, priv->io_base + _REG(L_HSYNC_VE_ADDR));
1745+
1746+
/* Vsync signal */
1747+
writel_relaxed(vso_begin, priv->io_base + _REG(L_VSYNC_HS_ADDR));
1748+
writel_relaxed(vso_end, priv->io_base + _REG(L_VSYNC_HE_ADDR));
1749+
writel_relaxed(vso_bline, priv->io_base + _REG(L_VSYNC_VS_ADDR));
1750+
writel_relaxed(vso_eline, priv->io_base + _REG(L_VSYNC_VE_ADDR));
1751+
1752+
writel_relaxed(0, priv->io_base + _REG(L_INV_CNT_ADDR));
1753+
writel_relaxed(L_TCON_MISC_SEL_STV1 | L_TCON_MISC_SEL_STV2,
1754+
priv->io_base + _REG(L_TCON_MISC_SEL_ADDR));
1755+
1756+
priv->venc.current_mode = MESON_VENC_MODE_MIPI_DSI;
1757+
}
1758+
EXPORT_SYMBOL_GPL(meson_venc_mipi_dsi_mode_set);
1759+
15601760
void meson_venci_cvbs_mode_set(struct meson_drm *priv,
15611761
struct meson_cvbs_enci_mode *mode)
15621762
{
@@ -1747,8 +1947,15 @@ unsigned int meson_venci_get_field(struct meson_drm *priv)
17471947

17481948
void meson_venc_enable_vsync(struct meson_drm *priv)
17491949
{
1750-
writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN,
1751-
priv->io_base + _REG(VENC_INTCTRL));
1950+
switch (priv->venc.current_mode) {
1951+
case MESON_VENC_MODE_MIPI_DSI:
1952+
writel_relaxed(VENC_INTCTRL_ENCP_LNRST_INT_EN,
1953+
priv->io_base + _REG(VENC_INTCTRL));
1954+
break;
1955+
default:
1956+
writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN,
1957+
priv->io_base + _REG(VENC_INTCTRL));
1958+
}
17521959
regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25));
17531960
}
17541961

‎drivers/gpu/drm/meson/meson_venc.h‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@ enum {
2121
MESON_VENC_MODE_CVBS_PAL,
2222
MESON_VENC_MODE_CVBS_NTSC,
2323
MESON_VENC_MODE_HDMI,
24+
MESON_VENC_MODE_MIPI_DSI,
2425
};
2526

2627
struct meson_cvbs_enci_mode {
@@ -47,6 +48,9 @@ struct meson_cvbs_enci_mode {
4748
unsigned int analog_sync_adj;
4849
};
4950

51+
/* LCD Encoder gamma setup */
52+
void meson_encl_load_gamma(struct meson_drm *priv);
53+
5054
/* HDMI Clock parameters */
5155
enum drm_mode_status
5256
meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode);
@@ -63,6 +67,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
6367
unsigned int ycrcb_map,
6468
bool yuv420_mode,
6569
const struct drm_display_mode *mode);
70+
void meson_venc_mipi_dsi_mode_set(struct meson_drm *priv,
71+
const struct drm_display_mode *mode);
6672
unsigned int meson_venci_get_field(struct meson_drm *priv);
6773

6874
void meson_venc_enable_vsync(struct meson_drm *priv);

‎drivers/gpu/drm/meson/meson_vpp.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,8 @@
1212
struct drm_rect;
1313
struct meson_drm;
1414

15+
/* Mux VIU/VPP to ENCL */
16+
#define MESON_VIU_VPP_MUX_ENCL 0x0
1517
/* Mux VIU/VPP to ENCI */
1618
#define MESON_VIU_VPP_MUX_ENCI 0x5
1719
/* Mux VIU/VPP to ENCP */

0 commit comments

Comments
 (0)