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ctmarinasctmarinas
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Merge branch 'for-next/sysreg' into for-next/core
* for-next/sysreg: : arm64 sysreg updates/cleanups arm64/sysreg: Remove unused define ARM64_FEATURE_FIELD_BITS KVM: arm64: selftests: Consider all 7 possible levels of cache KVM: arm64: selftests: Remove ARM64_FEATURE_FIELD_BITS and its last user arm64/sysreg: Add ICH_VMCR_EL2 arm64/sysreg: Move generation of RES0/RES1/UNKN to function arm64/sysreg: Support feature-specific fields with 'Prefix' descriptor arm64/sysreg: Fix checks for incomplete sysreg definitions arm64/sysreg: Replace TCR_EL1 field macros
2 parents 17c05cb + 27abb1e commit 52c4d1d

14 files changed

Lines changed: 211 additions & 177 deletions

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‎arch/arm64/include/asm/assembler.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -325,14 +325,14 @@ alternative_cb_end
325325
* tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map
326326
*/
327327
.macro tcr_set_t0sz, valreg, t0sz
328-
bfi \valreg, \t0sz, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
328+
bfi \valreg, \t0sz, #TCR_EL1_T0SZ_SHIFT, #TCR_EL1_T0SZ_WIDTH
329329
.endm
330330

331331
/*
332332
* tcr_set_t1sz - update TCR.T1SZ
333333
*/
334334
.macro tcr_set_t1sz, valreg, t1sz
335-
bfi \valreg, \t1sz, #TCR_T1SZ_OFFSET, #TCR_TxSZ_WIDTH
335+
bfi \valreg, \t1sz, #TCR_EL1_T1SZ_SHIFT, #TCR_EL1_T1SZ_WIDTH
336336
.endm
337337

338338
/*
@@ -589,7 +589,7 @@ alternative_endif
589589
.macro offset_ttbr1, ttbr, tmp
590590
#if defined(CONFIG_ARM64_VA_BITS_52) && !defined(CONFIG_ARM64_LPA2)
591591
mrs \tmp, tcr_el1
592-
and \tmp, \tmp, #TCR_T1SZ_MASK
592+
and \tmp, \tmp, #TCR_EL1_T1SZ_MASK
593593
cmp \tmp, #TCR_T1SZ(VA_BITS_MIN)
594594
orr \tmp, \ttbr, #TTBR1_BADDR_4852_OFFSET
595595
csel \ttbr, \tmp, \ttbr, eq

‎arch/arm64/include/asm/cputype.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -247,7 +247,7 @@
247247
/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
248248
#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
249249
#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
250-
#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
250+
#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_EL1_NFD1 | TCR_EL1_NFD0)
251251

252252
#ifndef __ASSEMBLER__
253253

‎arch/arm64/include/asm/mmu_context.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -68,10 +68,10 @@ static inline void __cpu_set_tcr_t0sz(unsigned long t0sz)
6868
{
6969
unsigned long tcr = read_sysreg(tcr_el1);
7070

71-
if ((tcr & TCR_T0SZ_MASK) == t0sz)
71+
if ((tcr & TCR_EL1_T0SZ_MASK) == t0sz)
7272
return;
7373

74-
tcr &= ~TCR_T0SZ_MASK;
74+
tcr &= ~TCR_EL1_T0SZ_MASK;
7575
tcr |= t0sz;
7676
write_sysreg(tcr, tcr_el1);
7777
isb();

‎arch/arm64/include/asm/pgtable-hwdef.h‎

Lines changed: 47 additions & 96 deletions
Original file line numberDiff line numberDiff line change
@@ -228,102 +228,53 @@
228228
/*
229229
* TCR flags.
230230
*/
231-
#define TCR_T0SZ_OFFSET 0
232-
#define TCR_T1SZ_OFFSET 16
233-
#define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
234-
#define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
235-
#define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x))
236-
#define TCR_TxSZ_WIDTH 6
237-
#define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
238-
#define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
239-
240-
#define TCR_EPD0_SHIFT 7
241-
#define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT)
242-
#define TCR_IRGN0_SHIFT 8
243-
#define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT)
244-
#define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT)
245-
#define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT)
246-
#define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT)
247-
#define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT)
248-
249-
#define TCR_EPD1_SHIFT 23
250-
#define TCR_EPD1_MASK (UL(1) << TCR_EPD1_SHIFT)
251-
#define TCR_IRGN1_SHIFT 24
252-
#define TCR_IRGN1_MASK (UL(3) << TCR_IRGN1_SHIFT)
253-
#define TCR_IRGN1_NC (UL(0) << TCR_IRGN1_SHIFT)
254-
#define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT)
255-
#define TCR_IRGN1_WT (UL(2) << TCR_IRGN1_SHIFT)
256-
#define TCR_IRGN1_WBnWA (UL(3) << TCR_IRGN1_SHIFT)
257-
258-
#define TCR_IRGN_NC (TCR_IRGN0_NC | TCR_IRGN1_NC)
259-
#define TCR_IRGN_WBWA (TCR_IRGN0_WBWA | TCR_IRGN1_WBWA)
260-
#define TCR_IRGN_WT (TCR_IRGN0_WT | TCR_IRGN1_WT)
261-
#define TCR_IRGN_WBnWA (TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA)
262-
#define TCR_IRGN_MASK (TCR_IRGN0_MASK | TCR_IRGN1_MASK)
263-
264-
265-
#define TCR_ORGN0_SHIFT 10
266-
#define TCR_ORGN0_MASK (UL(3) << TCR_ORGN0_SHIFT)
267-
#define TCR_ORGN0_NC (UL(0) << TCR_ORGN0_SHIFT)
268-
#define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT)
269-
#define TCR_ORGN0_WT (UL(2) << TCR_ORGN0_SHIFT)
270-
#define TCR_ORGN0_WBnWA (UL(3) << TCR_ORGN0_SHIFT)
271-
272-
#define TCR_ORGN1_SHIFT 26
273-
#define TCR_ORGN1_MASK (UL(3) << TCR_ORGN1_SHIFT)
274-
#define TCR_ORGN1_NC (UL(0) << TCR_ORGN1_SHIFT)
275-
#define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT)
276-
#define TCR_ORGN1_WT (UL(2) << TCR_ORGN1_SHIFT)
277-
#define TCR_ORGN1_WBnWA (UL(3) << TCR_ORGN1_SHIFT)
278-
279-
#define TCR_ORGN_NC (TCR_ORGN0_NC | TCR_ORGN1_NC)
280-
#define TCR_ORGN_WBWA (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)
281-
#define TCR_ORGN_WT (TCR_ORGN0_WT | TCR_ORGN1_WT)
282-
#define TCR_ORGN_WBnWA (TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA)
283-
#define TCR_ORGN_MASK (TCR_ORGN0_MASK | TCR_ORGN1_MASK)
284-
285-
#define TCR_SH0_SHIFT 12
286-
#define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT)
287-
#define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT)
288-
289-
#define TCR_SH1_SHIFT 28
290-
#define TCR_SH1_MASK (UL(3) << TCR_SH1_SHIFT)
291-
#define TCR_SH1_INNER (UL(3) << TCR_SH1_SHIFT)
292-
#define TCR_SHARED (TCR_SH0_INNER | TCR_SH1_INNER)
293-
294-
#define TCR_TG0_SHIFT 14
295-
#define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT)
296-
#define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT)
297-
#define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT)
298-
#define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT)
299-
300-
#define TCR_TG1_SHIFT 30
301-
#define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT)
302-
#define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT)
303-
#define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT)
304-
#define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT)
305-
306-
#define TCR_IPS_SHIFT 32
307-
#define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT)
308-
#define TCR_A1 (UL(1) << 22)
309-
#define TCR_ASID16 (UL(1) << 36)
310-
#define TCR_TBI0 (UL(1) << 37)
311-
#define TCR_TBI1 (UL(1) << 38)
312-
#define TCR_HA (UL(1) << 39)
313-
#define TCR_HD (UL(1) << 40)
314-
#define TCR_HPD0_SHIFT 41
315-
#define TCR_HPD0 (UL(1) << TCR_HPD0_SHIFT)
316-
#define TCR_HPD1_SHIFT 42
317-
#define TCR_HPD1 (UL(1) << TCR_HPD1_SHIFT)
318-
#define TCR_TBID0 (UL(1) << 51)
319-
#define TCR_TBID1 (UL(1) << 52)
320-
#define TCR_NFD0 (UL(1) << 53)
321-
#define TCR_NFD1 (UL(1) << 54)
322-
#define TCR_E0PD0 (UL(1) << 55)
323-
#define TCR_E0PD1 (UL(1) << 56)
324-
#define TCR_TCMA0 (UL(1) << 57)
325-
#define TCR_TCMA1 (UL(1) << 58)
326-
#define TCR_DS (UL(1) << 59)
231+
#define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_EL1_T0SZ_SHIFT)
232+
#define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_EL1_T1SZ_SHIFT)
233+
234+
#define TCR_T0SZ_MASK TCR_EL1_T0SZ_MASK
235+
#define TCR_T1SZ_MASK TCR_EL1_T1SZ_MASK
236+
237+
#define TCR_EPD0_MASK TCR_EL1_EPD0_MASK
238+
#define TCR_EPD1_MASK TCR_EL1_EPD1_MASK
239+
240+
#define TCR_IRGN0_MASK TCR_EL1_IRGN0_MASK
241+
#define TCR_IRGN0_WBWA (TCR_EL1_IRGN0_WBWA << TCR_EL1_IRGN0_SHIFT)
242+
243+
#define TCR_ORGN0_MASK TCR_EL1_ORGN0_MASK
244+
#define TCR_ORGN0_WBWA (TCR_EL1_ORGN0_WBWA << TCR_EL1_ORGN0_SHIFT)
245+
246+
#define TCR_SH0_MASK TCR_EL1_SH0_MASK
247+
#define TCR_SH0_INNER (TCR_EL1_SH0_INNER << TCR_EL1_SH0_SHIFT)
248+
249+
#define TCR_SH1_MASK TCR_EL1_SH1_MASK
250+
251+
#define TCR_TG0_SHIFT TCR_EL1_TG0_SHIFT
252+
#define TCR_TG0_MASK TCR_EL1_TG0_MASK
253+
#define TCR_TG0_4K (TCR_EL1_TG0_4K << TCR_EL1_TG0_SHIFT)
254+
#define TCR_TG0_64K (TCR_EL1_TG0_64K << TCR_EL1_TG0_SHIFT)
255+
#define TCR_TG0_16K (TCR_EL1_TG0_16K << TCR_EL1_TG0_SHIFT)
256+
257+
#define TCR_TG1_SHIFT TCR_EL1_TG1_SHIFT
258+
#define TCR_TG1_MASK TCR_EL1_TG1_MASK
259+
#define TCR_TG1_16K (TCR_EL1_TG1_16K << TCR_EL1_TG1_SHIFT)
260+
#define TCR_TG1_4K (TCR_EL1_TG1_4K << TCR_EL1_TG1_SHIFT)
261+
#define TCR_TG1_64K (TCR_EL1_TG1_64K << TCR_EL1_TG1_SHIFT)
262+
263+
#define TCR_IPS_SHIFT TCR_EL1_IPS_SHIFT
264+
#define TCR_IPS_MASK TCR_EL1_IPS_MASK
265+
#define TCR_A1 TCR_EL1_A1
266+
#define TCR_ASID16 TCR_EL1_AS
267+
#define TCR_TBI0 TCR_EL1_TBI0
268+
#define TCR_TBI1 TCR_EL1_TBI1
269+
#define TCR_HA TCR_EL1_HA
270+
#define TCR_HD TCR_EL1_HD
271+
#define TCR_HPD0 TCR_EL1_HPD0
272+
#define TCR_HPD1 TCR_EL1_HPD1
273+
#define TCR_TBID0 TCR_EL1_TBID0
274+
#define TCR_TBID1 TCR_EL1_TBID1
275+
#define TCR_E0PD0 TCR_EL1_E0PD0
276+
#define TCR_E0PD1 TCR_EL1_E0PD1
277+
#define TCR_DS TCR_EL1_DS
327278

328279
/*
329280
* TTBR.

‎arch/arm64/include/asm/pgtable-prot.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,7 @@ extern unsigned long prot_ns_shared;
8484
#else
8585
static inline bool __pure lpa2_is_enabled(void)
8686
{
87-
return read_tcr() & TCR_DS;
87+
return read_tcr() & TCR_EL1_DS;
8888
}
8989

9090
#define PTE_MAYBE_SHARED (lpa2_is_enabled() ? 0 : PTE_SHARED)

‎arch/arm64/include/asm/sysreg.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1129,8 +1129,6 @@
11291129
#define gicr_insn(insn) read_sysreg_s(GICV5_OP_GICR_##insn)
11301130
#define gic_insn(v, insn) write_sysreg_s(v, GICV5_OP_GIC_##insn)
11311131

1132-
#define ARM64_FEATURE_FIELD_BITS 4
1133-
11341132
#ifdef __ASSEMBLER__
11351133

11361134
.macro mrs_s, rt, sreg

‎arch/arm64/kernel/cpufeature.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1969,7 +1969,7 @@ static struct cpumask dbm_cpus __read_mostly;
19691969

19701970
static inline void __cpu_enable_hw_dbm(void)
19711971
{
1972-
u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1972+
u64 tcr = read_sysreg(tcr_el1) | TCR_EL1_HD;
19731973

19741974
write_sysreg(tcr, tcr_el1);
19751975
isb();
@@ -2255,7 +2255,7 @@ static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
22552255
static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
22562256
{
22572257
if (this_cpu_has_cap(ARM64_HAS_E0PD))
2258-
sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
2258+
sysreg_clear_set(tcr_el1, 0, TCR_EL1_E0PD1);
22592259
}
22602260
#endif /* CONFIG_ARM64_E0PD */
22612261

‎arch/arm64/kernel/pi/map_kernel.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -141,13 +141,13 @@ static void __init map_kernel(u64 kaslr_offset, u64 va_offset, int root_level)
141141
static void noinline __section(".idmap.text") set_ttbr0_for_lpa2(phys_addr_t ttbr)
142142
{
143143
u64 sctlr = read_sysreg(sctlr_el1);
144-
u64 tcr = read_sysreg(tcr_el1) | TCR_DS;
144+
u64 tcr = read_sysreg(tcr_el1) | TCR_EL1_DS;
145145
u64 mmfr0 = read_sysreg(id_aa64mmfr0_el1);
146146
u64 parange = cpuid_feature_extract_unsigned_field(mmfr0,
147147
ID_AA64MMFR0_EL1_PARANGE_SHIFT);
148148

149-
tcr &= ~TCR_IPS_MASK;
150-
tcr |= parange << TCR_IPS_SHIFT;
149+
tcr &= ~TCR_EL1_IPS_MASK;
150+
tcr |= parange << TCR_EL1_IPS_SHIFT;
151151

152152
asm(" msr sctlr_el1, %0 ;"
153153
" isb ;"
@@ -263,7 +263,7 @@ asmlinkage void __init early_map_kernel(u64 boot_status, phys_addr_t fdt)
263263
}
264264

265265
if (va_bits > VA_BITS_MIN)
266-
sysreg_clear_set(tcr_el1, TCR_T1SZ_MASK, TCR_T1SZ(va_bits));
266+
sysreg_clear_set(tcr_el1, TCR_EL1_T1SZ_MASK, TCR_T1SZ(va_bits));
267267

268268
/*
269269
* The virtual KASLR displacement modulo 2MiB is decided by the

‎arch/arm64/kernel/vmcore_info.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ static inline u64 get_tcr_el1_t1sz(void);
1414

1515
static inline u64 get_tcr_el1_t1sz(void)
1616
{
17-
return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET;
17+
return (read_sysreg(tcr_el1) & TCR_EL1_T1SZ_MASK) >> TCR_EL1_T1SZ_SHIFT;
1818
}
1919

2020
void arch_crash_save_vmcoreinfo(void)

‎arch/arm64/mm/proc.S‎

Lines changed: 23 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -23,15 +23,18 @@
2323
#include <asm/sysreg.h>
2424

2525
#ifdef CONFIG_ARM64_64K_PAGES
26-
#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
26+
#define TCR_TG_FLAGS ((TCR_EL1_TG0_64K << TCR_EL1_TG0_SHIFT) |\
27+
(TCR_EL1_TG1_64K << TCR_EL1_TG1_SHIFT))
2728
#elif defined(CONFIG_ARM64_16K_PAGES)
28-
#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K
29+
#define TCR_TG_FLAGS ((TCR_EL1_TG0_16K << TCR_EL1_TG0_SHIFT) |\
30+
(TCR_EL1_TG1_16K << TCR_EL1_TG1_SHIFT))
2931
#else /* CONFIG_ARM64_4K_PAGES */
30-
#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
32+
#define TCR_TG_FLAGS ((TCR_EL1_TG0_4K << TCR_EL1_TG0_SHIFT) |\
33+
(TCR_EL1_TG1_4K << TCR_EL1_TG1_SHIFT))
3134
#endif
3235

3336
#ifdef CONFIG_RANDOMIZE_BASE
34-
#define TCR_KASLR_FLAGS TCR_NFD1
37+
#define TCR_KASLR_FLAGS TCR_EL1_NFD1
3538
#else
3639
#define TCR_KASLR_FLAGS 0
3740
#endif
@@ -40,23 +43,30 @@
4043
#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
4144

4245
#ifdef CONFIG_KASAN_SW_TAGS
43-
#define TCR_KASAN_SW_FLAGS TCR_TBI1 | TCR_TBID1
46+
#define TCR_KASAN_SW_FLAGS TCR_EL1_TBI1 | TCR_EL1_TBID1
4447
#else
4548
#define TCR_KASAN_SW_FLAGS 0
4649
#endif
4750

4851
#ifdef CONFIG_KASAN_HW_TAGS
49-
#define TCR_MTE_FLAGS TCR_TCMA1 | TCR_TBI1 | TCR_TBID1
52+
#define TCR_MTE_FLAGS TCR_EL1_TCMA1 | TCR_EL1_TBI1 | TCR_EL1_TBID1
5053
#elif defined(CONFIG_ARM64_MTE)
5154
/*
5255
* The mte_zero_clear_page_tags() implementation uses DC GZVA, which relies on
5356
* TBI being enabled at EL1.
5457
*/
55-
#define TCR_MTE_FLAGS TCR_TBI1 | TCR_TBID1
58+
#define TCR_MTE_FLAGS TCR_EL1_TBI1 | TCR_EL1_TBID1
5659
#else
5760
#define TCR_MTE_FLAGS 0
5861
#endif
5962

63+
#define TCR_IRGN_WBWA ((TCR_EL1_IRGN0_WBWA << TCR_EL1_IRGN0_SHIFT) |\
64+
(TCR_EL1_IRGN1_WBWA << TCR_EL1_IRGN1_SHIFT))
65+
#define TCR_ORGN_WBWA ((TCR_EL1_ORGN0_WBWA << TCR_EL1_ORGN0_SHIFT) |\
66+
(TCR_EL1_ORGN1_WBWA << TCR_EL1_ORGN1_SHIFT))
67+
#define TCR_SHARED ((TCR_EL1_SH0_INNER << TCR_EL1_SH0_SHIFT) |\
68+
(TCR_EL1_SH1_INNER << TCR_EL1_SH1_SHIFT))
69+
6070
/*
6171
* Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
6272
* changed during mte_cpu_setup to Normal Tagged if the system supports MTE.
@@ -129,7 +139,7 @@ SYM_FUNC_START(cpu_do_resume)
129139

130140
/* Don't change t0sz here, mask those bits when restoring */
131141
mrs x7, tcr_el1
132-
bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
142+
bfi x8, x7, TCR_EL1_T0SZ_SHIFT, TCR_EL1_T0SZ_WIDTH
133143

134144
msr tcr_el1, x8
135145
msr vbar_el1, x9
@@ -481,8 +491,8 @@ SYM_FUNC_START(__cpu_setup)
481491
tcr2 .req x15
482492
mov_q mair, MAIR_EL1_SET
483493
mov_q tcr, TCR_T0SZ(IDMAP_VA_BITS) | TCR_T1SZ(VA_BITS_MIN) | TCR_CACHE_FLAGS | \
484-
TCR_SHARED | TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
485-
TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS | TCR_MTE_FLAGS
494+
TCR_SHARED | TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_EL1_AS | \
495+
TCR_EL1_TBI0 | TCR_EL1_A1 | TCR_KASAN_SW_FLAGS | TCR_MTE_FLAGS
486496
mov tcr2, xzr
487497

488498
tcr_clear_errata_bits tcr, x9, x5
@@ -492,15 +502,15 @@ SYM_FUNC_START(__cpu_setup)
492502
alternative_if ARM64_HAS_VA52
493503
tcr_set_t1sz tcr, x9
494504
#ifdef CONFIG_ARM64_LPA2
495-
orr tcr, tcr, #TCR_DS
505+
orr tcr, tcr, #TCR_EL1_DS
496506
#endif
497507
alternative_else_nop_endif
498508
#endif
499509

500510
/*
501511
* Set the IPS bits in TCR_EL1.
502512
*/
503-
tcr_compute_pa_size tcr, #TCR_IPS_SHIFT, x5, x6
513+
tcr_compute_pa_size tcr, #TCR_EL1_IPS_SHIFT, x5, x6
504514
#ifdef CONFIG_ARM64_HW_AFDBM
505515
/*
506516
* Enable hardware update of the Access Flags bit.
@@ -510,7 +520,7 @@ alternative_else_nop_endif
510520
mrs x9, ID_AA64MMFR1_EL1
511521
ubfx x9, x9, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, #4
512522
cbz x9, 1f
513-
orr tcr, tcr, #TCR_HA // hardware Access flag update
523+
orr tcr, tcr, #TCR_EL1_HA // hardware Access flag update
514524
#ifdef CONFIG_ARM64_HAFT
515525
cmp x9, ID_AA64MMFR1_EL1_HAFDBS_HAFT
516526
b.lt 1f

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