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cometzerobebarino
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dt-bindings: clock: exynosautov9: correct count of NR_CLK
_NR_CLKS which can be used to register clocks via nr_clk_ids. The clock IDs are started from 1. So, _NR_CLKS should be defined to "the last clock id + 1" Fixes: 680e1c8 ("dt-bindings: clock: add clock binding definitions for Exynos Auto v9") Signed-off-by: Chanho Park <chanho61.park@samsung.com> Link: https://lore.kernel.org/r/20220520030625.145324-1-chanho61.park@samsung.com Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Lines changed: 7 additions & 7 deletions

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include/dt-bindings/clock/samsung,exynosautov9.h

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -166,15 +166,15 @@
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#define GOUT_CLKCMU_PERIC1_IP 248
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#define GOUT_CLKCMU_PERIS_BUS 249
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169-
#define TOP_NR_CLK 249
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#define TOP_NR_CLK 250
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/* CMU_BUSMC */
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#define CLK_MOUT_BUSMC_BUS_USER 1
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#define CLK_DOUT_BUSMC_BUSP 2
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#define CLK_GOUT_BUSMC_PDMA0_PCLK 3
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#define CLK_GOUT_BUSMC_SPDMA_PCLK 4
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177-
#define BUSMC_NR_CLK 4
177+
#define BUSMC_NR_CLK 5
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/* CMU_CORE */
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#define CLK_MOUT_CORE_BUS_USER 1
@@ -183,7 +183,7 @@
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#define CLK_GOUT_CORE_CCI_PCLK 4
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#define CLK_GOUT_CORE_CMU_CORE_PCLK 5
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186-
#define CORE_NR_CLK 5
186+
#define CORE_NR_CLK 6
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/* CMU_FSYS2 */
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#define CLK_MOUT_FSYS2_BUS_USER 1
@@ -194,7 +194,7 @@
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#define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK 6
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#define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO 7
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197-
#define FSYS2_NR_CLK 7
197+
#define FSYS2_NR_CLK 8
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/* CMU_PERIC0 */
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#define CLK_MOUT_PERIC0_BUS_USER 1
@@ -240,7 +240,7 @@
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#define CLK_GOUT_PERIC0_PCLK_10 41
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#define CLK_GOUT_PERIC0_PCLK_11 42
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243-
#define PERIC0_NR_CLK 42
243+
#define PERIC0_NR_CLK 43
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/* CMU_PERIC1 */
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#define CLK_MOUT_PERIC1_BUS_USER 1
@@ -286,14 +286,14 @@
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#define CLK_GOUT_PERIC1_PCLK_10 41
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#define CLK_GOUT_PERIC1_PCLK_11 42
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#define PERIC1_NR_CLK 42
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#define PERIC1_NR_CLK 43
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/* CMU_PERIS */
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#define CLK_MOUT_PERIS_BUS_USER 1
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#define CLK_GOUT_SYSREG_PERIS_PCLK 2
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#define CLK_GOUT_WDT_CLUSTER0 3
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#define CLK_GOUT_WDT_CLUSTER1 4
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297-
#define PERIS_NR_CLK 4
297+
#define PERIS_NR_CLK 5
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#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */

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