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torvaldstorvalds
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd: "A couple driver fixes in the clk subsystem - Fix a hang due to bad clk parent in the Ingenic jz4725b driver - Fix SD controllers on Qualcomm MSM8994 SoCs by removing clks that shouldn't be touched" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: jz4725b: fix mmc0 clock gating clk: qcom: gcc-msm8994: Remove NoC clocks
2 parents 5ee3d00 + 2f0754f commit 53ab78c

2 files changed

Lines changed: 10 additions & 99 deletions

File tree

‎drivers/clk/ingenic/jz4725b-cgu.c‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -139,11 +139,10 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
139139
},
140140

141141
[JZ4725B_CLK_I2S] = {
142-
"i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
142+
"i2s", CGU_CLK_MUX | CGU_CLK_DIV,
143143
.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
144144
.mux = { CGU_REG_CPCCR, 31, 1 },
145145
.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
146-
.gate = { CGU_REG_CLKGR, 6 },
147146
},
148147

149148
[JZ4725B_CLK_SPI] = {

‎drivers/clk/qcom/gcc-msm8994.c‎

Lines changed: 9 additions & 97 deletions
Original file line numberDiff line numberDiff line change
@@ -108,42 +108,6 @@ static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
108108
{ .hw = &gpll4.clkr.hw },
109109
};
110110

111-
static struct clk_rcg2 system_noc_clk_src = {
112-
.cmd_rcgr = 0x0120,
113-
.hid_width = 5,
114-
.parent_map = gcc_xo_gpll0_map,
115-
.clkr.hw.init = &(struct clk_init_data){
116-
.name = "system_noc_clk_src",
117-
.parent_data = gcc_xo_gpll0,
118-
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
119-
.ops = &clk_rcg2_ops,
120-
},
121-
};
122-
123-
static struct clk_rcg2 config_noc_clk_src = {
124-
.cmd_rcgr = 0x0150,
125-
.hid_width = 5,
126-
.parent_map = gcc_xo_gpll0_map,
127-
.clkr.hw.init = &(struct clk_init_data){
128-
.name = "config_noc_clk_src",
129-
.parent_data = gcc_xo_gpll0,
130-
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
131-
.ops = &clk_rcg2_ops,
132-
},
133-
};
134-
135-
static struct clk_rcg2 periph_noc_clk_src = {
136-
.cmd_rcgr = 0x0190,
137-
.hid_width = 5,
138-
.parent_map = gcc_xo_gpll0_map,
139-
.clkr.hw.init = &(struct clk_init_data){
140-
.name = "periph_noc_clk_src",
141-
.parent_data = gcc_xo_gpll0,
142-
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
143-
.ops = &clk_rcg2_ops,
144-
},
145-
};
146-
147111
static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
148112
F(50000000, P_GPLL0, 12, 0, 0),
149113
F(100000000, P_GPLL0, 6, 0, 0),
@@ -1150,8 +1114,6 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
11501114
.enable_mask = BIT(17),
11511115
.hw.init = &(struct clk_init_data){
11521116
.name = "gcc_blsp1_ahb_clk",
1153-
.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
1154-
.num_parents = 1,
11551117
.ops = &clk_branch2_ops,
11561118
},
11571119
},
@@ -1435,8 +1397,6 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
14351397
.enable_mask = BIT(15),
14361398
.hw.init = &(struct clk_init_data){
14371399
.name = "gcc_blsp2_ahb_clk",
1438-
.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
1439-
.num_parents = 1,
14401400
.ops = &clk_branch2_ops,
14411401
},
14421402
},
@@ -1764,8 +1724,6 @@ static struct clk_branch gcc_lpass_q6_axi_clk = {
17641724
.enable_mask = BIT(0),
17651725
.hw.init = &(struct clk_init_data){
17661726
.name = "gcc_lpass_q6_axi_clk",
1767-
.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
1768-
.num_parents = 1,
17691727
.ops = &clk_branch2_ops,
17701728
},
17711729
},
@@ -1778,8 +1736,6 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
17781736
.enable_mask = BIT(0),
17791737
.hw.init = &(struct clk_init_data){
17801738
.name = "gcc_mss_q6_bimc_axi_clk",
1781-
.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
1782-
.num_parents = 1,
17831739
.ops = &clk_branch2_ops,
17841740
},
17851741
},
@@ -1807,9 +1763,6 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
18071763
.enable_mask = BIT(0),
18081764
.hw.init = &(struct clk_init_data){
18091765
.name = "gcc_pcie_0_cfg_ahb_clk",
1810-
.parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw },
1811-
.num_parents = 1,
1812-
.flags = CLK_SET_RATE_PARENT,
18131766
.ops = &clk_branch2_ops,
18141767
},
18151768
},
@@ -1822,9 +1775,6 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
18221775
.enable_mask = BIT(0),
18231776
.hw.init = &(struct clk_init_data){
18241777
.name = "gcc_pcie_0_mstr_axi_clk",
1825-
.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
1826-
.num_parents = 1,
1827-
.flags = CLK_SET_RATE_PARENT,
18281778
.ops = &clk_branch2_ops,
18291779
},
18301780
},
@@ -1854,9 +1804,6 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
18541804
.enable_mask = BIT(0),
18551805
.hw.init = &(struct clk_init_data){
18561806
.name = "gcc_pcie_0_slv_axi_clk",
1857-
.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
1858-
.num_parents = 1,
1859-
.flags = CLK_SET_RATE_PARENT,
18601807
.ops = &clk_branch2_ops,
18611808
},
18621809
},
@@ -1884,9 +1831,6 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
18841831
.enable_mask = BIT(0),
18851832
.hw.init = &(struct clk_init_data){
18861833
.name = "gcc_pcie_1_cfg_ahb_clk",
1887-
.parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw },
1888-
.num_parents = 1,
1889-
.flags = CLK_SET_RATE_PARENT,
18901834
.ops = &clk_branch2_ops,
18911835
},
18921836
},
@@ -1899,9 +1843,6 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
18991843
.enable_mask = BIT(0),
19001844
.hw.init = &(struct clk_init_data){
19011845
.name = "gcc_pcie_1_mstr_axi_clk",
1902-
.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
1903-
.num_parents = 1,
1904-
.flags = CLK_SET_RATE_PARENT,
19051846
.ops = &clk_branch2_ops,
19061847
},
19071848
},
@@ -1930,9 +1871,6 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
19301871
.enable_mask = BIT(0),
19311872
.hw.init = &(struct clk_init_data){
19321873
.name = "gcc_pcie_1_slv_axi_clk",
1933-
.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
1934-
.num_parents = 1,
1935-
.flags = CLK_SET_RATE_PARENT,
19361874
.ops = &clk_branch2_ops,
19371875
},
19381876
},
@@ -1960,8 +1898,6 @@ static struct clk_branch gcc_pdm_ahb_clk = {
19601898
.enable_mask = BIT(0),
19611899
.hw.init = &(struct clk_init_data){
19621900
.name = "gcc_pdm_ahb_clk",
1963-
.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
1964-
.num_parents = 1,
19651901
.ops = &clk_branch2_ops,
19661902
},
19671903
},
@@ -1989,9 +1925,6 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
19891925
.enable_mask = BIT(0),
19901926
.hw.init = &(struct clk_init_data){
19911927
.name = "gcc_sdcc1_ahb_clk",
1992-
.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
1993-
.num_parents = 1,
1994-
.flags = CLK_SET_RATE_PARENT,
19951928
.ops = &clk_branch2_ops,
19961929
},
19971930
},
@@ -2004,9 +1937,6 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
20041937
.enable_mask = BIT(0),
20051938
.hw.init = &(struct clk_init_data){
20061939
.name = "gcc_sdcc2_ahb_clk",
2007-
.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
2008-
.num_parents = 1,
2009-
.flags = CLK_SET_RATE_PARENT,
20101940
.ops = &clk_branch2_ops,
20111941
},
20121942
},
@@ -2034,9 +1964,6 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
20341964
.enable_mask = BIT(0),
20351965
.hw.init = &(struct clk_init_data){
20361966
.name = "gcc_sdcc3_ahb_clk",
2037-
.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
2038-
.num_parents = 1,
2039-
.flags = CLK_SET_RATE_PARENT,
20401967
.ops = &clk_branch2_ops,
20411968
},
20421969
},
@@ -2064,9 +1991,6 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
20641991
.enable_mask = BIT(0),
20651992
.hw.init = &(struct clk_init_data){
20661993
.name = "gcc_sdcc4_ahb_clk",
2067-
.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
2068-
.num_parents = 1,
2069-
.flags = CLK_SET_RATE_PARENT,
20701994
.ops = &clk_branch2_ops,
20711995
},
20721996
},
@@ -2124,8 +2048,6 @@ static struct clk_branch gcc_tsif_ahb_clk = {
21242048
.enable_mask = BIT(0),
21252049
.hw.init = &(struct clk_init_data){
21262050
.name = "gcc_tsif_ahb_clk",
2127-
.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
2128-
.num_parents = 1,
21292051
.ops = &clk_branch2_ops,
21302052
},
21312053
},
@@ -2153,8 +2075,6 @@ static struct clk_branch gcc_ufs_ahb_clk = {
21532075
.enable_mask = BIT(0),
21542076
.hw.init = &(struct clk_init_data){
21552077
.name = "gcc_ufs_ahb_clk",
2156-
.parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw },
2157-
.num_parents = 1,
21582078
.ops = &clk_branch2_ops,
21592079
},
21602080
},
@@ -2198,8 +2118,6 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
21982118
.enable_mask = BIT(0),
21992119
.hw.init = &(struct clk_init_data){
22002120
.name = "gcc_ufs_rx_symbol_0_clk",
2201-
.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
2202-
.num_parents = 1,
22032121
.ops = &clk_branch2_ops,
22042122
},
22052123
},
@@ -2213,8 +2131,6 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
22132131
.enable_mask = BIT(0),
22142132
.hw.init = &(struct clk_init_data){
22152133
.name = "gcc_ufs_rx_symbol_1_clk",
2216-
.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
2217-
.num_parents = 1,
22182134
.ops = &clk_branch2_ops,
22192135
},
22202136
},
@@ -2243,8 +2159,6 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
22432159
.enable_mask = BIT(0),
22442160
.hw.init = &(struct clk_init_data){
22452161
.name = "gcc_ufs_tx_symbol_0_clk",
2246-
.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
2247-
.num_parents = 1,
22482162
.ops = &clk_branch2_ops,
22492163
},
22502164
},
@@ -2258,8 +2172,6 @@ static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
22582172
.enable_mask = BIT(0),
22592173
.hw.init = &(struct clk_init_data){
22602174
.name = "gcc_ufs_tx_symbol_1_clk",
2261-
.parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
2262-
.num_parents = 1,
22632175
.ops = &clk_branch2_ops,
22642176
},
22652177
},
@@ -2364,8 +2276,6 @@ static struct clk_branch gcc_usb_hs_ahb_clk = {
23642276
.enable_mask = BIT(0),
23652277
.hw.init = &(struct clk_init_data){
23662278
.name = "gcc_usb_hs_ahb_clk",
2367-
.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
2368-
.num_parents = 1,
23692279
.ops = &clk_branch2_ops,
23702280
},
23712281
},
@@ -2488,8 +2398,6 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
24882398
.enable_mask = BIT(10),
24892399
.hw.init = &(struct clk_init_data){
24902400
.name = "gcc_boot_rom_ahb_clk",
2491-
.parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw },
2492-
.num_parents = 1,
24932401
.ops = &clk_branch2_ops,
24942402
},
24952403
},
@@ -2503,8 +2411,6 @@ static struct clk_branch gcc_prng_ahb_clk = {
25032411
.enable_mask = BIT(13),
25042412
.hw.init = &(struct clk_init_data){
25052413
.name = "gcc_prng_ahb_clk",
2506-
.parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
2507-
.num_parents = 1,
25082414
.ops = &clk_branch2_ops,
25092415
},
25102416
},
@@ -2547,9 +2453,6 @@ static struct clk_regmap *gcc_msm8994_clocks[] = {
25472453
[GPLL0] = &gpll0.clkr,
25482454
[GPLL4_EARLY] = &gpll4_early.clkr,
25492455
[GPLL4] = &gpll4.clkr,
2550-
[CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
2551-
[PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
2552-
[SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
25532456
[UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
25542457
[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
25552458
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
@@ -2696,6 +2599,15 @@ static struct clk_regmap *gcc_msm8994_clocks[] = {
26962599
[USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr,
26972600
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
26982601
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2602+
2603+
/*
2604+
* The following clocks should NOT be managed by this driver, but they once were
2605+
* mistakengly added. Now they are only here to indicate that they are not defined
2606+
* on purpose, even though the names will stay in the header file (for ABI sanity).
2607+
*/
2608+
[CONFIG_NOC_CLK_SRC] = NULL,
2609+
[PERIPH_NOC_CLK_SRC] = NULL,
2610+
[SYSTEM_NOC_CLK_SRC] = NULL,
26992611
};
27002612

27012613
static struct gdsc *gcc_msm8994_gdscs[] = {

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