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phy: qcom: qmp: move common functions to common header
Move common init tables code to the common header phy-qcom-qmp-common.h. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-3-a463d0b57836@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
1 parent d3e7e79 commit 53d7776

7 files changed

Lines changed: 120 additions & 348 deletions

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‎drivers/phy/qualcomm/phy-qcom-qmp-combo.c‎

Lines changed: 16 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,8 @@
2525

2626
#include <dt-bindings/phy/phy-qcom-qmp.h>
2727

28+
#include "phy-qcom-qmp-common.h"
29+
2830
#include "phy-qcom-qmp.h"
2931
#include "phy-qcom-qmp-pcs-misc-v3.h"
3032
#include "phy-qcom-qmp-pcs-usb-v4.h"
@@ -72,30 +74,6 @@
7274

7375
#define PHY_INIT_COMPLETE_TIMEOUT 10000
7476

75-
struct qmp_phy_init_tbl {
76-
unsigned int offset;
77-
unsigned int val;
78-
/*
79-
* mask of lanes for which this register is written
80-
* for cases when second lane needs different values
81-
*/
82-
u8 lane_mask;
83-
};
84-
85-
#define QMP_PHY_INIT_CFG(o, v) \
86-
{ \
87-
.offset = o, \
88-
.val = v, \
89-
.lane_mask = 0xff, \
90-
}
91-
92-
#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
93-
{ \
94-
.offset = o, \
95-
.val = v, \
96-
.lane_mask = l, \
97-
}
98-
9977
/* set of registers with offsets different per-PHY */
10078
enum qphy_reg_layout {
10179
/* PCS registers */
@@ -2031,55 +2009,29 @@ static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = {
20312009
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
20322010
};
20332011

2034-
static void qmp_combo_configure_lane(void __iomem *base,
2035-
const struct qmp_phy_init_tbl tbl[],
2036-
int num,
2037-
u8 lane_mask)
2038-
{
2039-
int i;
2040-
const struct qmp_phy_init_tbl *t = tbl;
2041-
2042-
if (!t)
2043-
return;
2044-
2045-
for (i = 0; i < num; i++, t++) {
2046-
if (!(t->lane_mask & lane_mask))
2047-
continue;
2048-
2049-
writel(t->val, base + t->offset);
2050-
}
2051-
}
2052-
2053-
static void qmp_combo_configure(void __iomem *base,
2054-
const struct qmp_phy_init_tbl tbl[],
2055-
int num)
2056-
{
2057-
qmp_combo_configure_lane(base, tbl, num, 0xff);
2058-
}
2059-
20602012
static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp)
20612013
{
20622014
const struct qmp_phy_cfg *cfg = qmp->cfg;
20632015
void __iomem *serdes = qmp->dp_serdes;
20642016
const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
20652017

2066-
qmp_combo_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num);
2018+
qmp_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num);
20672019

20682020
switch (dp_opts->link_rate) {
20692021
case 1620:
2070-
qmp_combo_configure(serdes, cfg->serdes_tbl_rbr,
2022+
qmp_configure(serdes, cfg->serdes_tbl_rbr,
20712023
cfg->serdes_tbl_rbr_num);
20722024
break;
20732025
case 2700:
2074-
qmp_combo_configure(serdes, cfg->serdes_tbl_hbr,
2026+
qmp_configure(serdes, cfg->serdes_tbl_hbr,
20752027
cfg->serdes_tbl_hbr_num);
20762028
break;
20772029
case 5400:
2078-
qmp_combo_configure(serdes, cfg->serdes_tbl_hbr2,
2030+
qmp_configure(serdes, cfg->serdes_tbl_hbr2,
20792031
cfg->serdes_tbl_hbr2_num);
20802032
break;
20812033
case 8100:
2082-
qmp_combo_configure(serdes, cfg->serdes_tbl_hbr3,
2034+
qmp_configure(serdes, cfg->serdes_tbl_hbr3,
20832035
cfg->serdes_tbl_hbr3_num);
20842036
break;
20852037
default:
@@ -2681,8 +2633,8 @@ static int qmp_combo_dp_power_on(struct phy *phy)
26812633

26822634
qmp_combo_dp_serdes_init(qmp);
26832635

2684-
qmp_combo_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1);
2685-
qmp_combo_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2);
2636+
qmp_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1);
2637+
qmp_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2);
26862638

26872639
/* Configure special DP tx tunings */
26882640
cfg->configure_dp_tx(qmp);
@@ -2724,7 +2676,7 @@ static int qmp_combo_usb_power_on(struct phy *phy)
27242676
unsigned int val;
27252677
int ret;
27262678

2727-
qmp_combo_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num);
2679+
qmp_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num);
27282680

27292681
ret = clk_prepare_enable(qmp->pipe_clk);
27302682
if (ret) {
@@ -2733,16 +2685,16 @@ static int qmp_combo_usb_power_on(struct phy *phy)
27332685
}
27342686

27352687
/* Tx, Rx, and PCS configurations */
2736-
qmp_combo_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
2737-
qmp_combo_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
2688+
qmp_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
2689+
qmp_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
27382690

2739-
qmp_combo_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
2740-
qmp_combo_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
2691+
qmp_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
2692+
qmp_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
27412693

2742-
qmp_combo_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
2694+
qmp_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
27432695

27442696
if (pcs_usb)
2745-
qmp_combo_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num);
2697+
qmp_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num);
27462698

27472699
if (cfg->has_pwrdn_delay)
27482700
usleep_range(10, 20);

‎drivers/phy/qualcomm/phy-qcom-qmp-common.h‎

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
/* SPDX-License-Identifier: GPL-2.0 */
2+
/*
3+
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
4+
*/
5+
6+
#ifndef QCOM_PHY_QMP_COMMON_H_
7+
#define QCOM_PHY_QMP_COMMON_H_
8+
9+
struct qmp_phy_init_tbl {
10+
unsigned int offset;
11+
unsigned int val;
12+
/*
13+
* mask of lanes for which this register is written
14+
* for cases when second lane needs different values
15+
*/
16+
u8 lane_mask;
17+
};
18+
19+
#define QMP_PHY_INIT_CFG(o, v) \
20+
{ \
21+
.offset = o, \
22+
.val = v, \
23+
.lane_mask = 0xff, \
24+
}
25+
26+
#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
27+
{ \
28+
.offset = o, \
29+
.val = v, \
30+
.lane_mask = l, \
31+
}
32+
33+
static inline void qmp_configure_lane(void __iomem *base,
34+
const struct qmp_phy_init_tbl tbl[],
35+
int num,
36+
u8 lane_mask)
37+
{
38+
int i;
39+
const struct qmp_phy_init_tbl *t = tbl;
40+
41+
if (!t)
42+
return;
43+
44+
for (i = 0; i < num; i++, t++) {
45+
if (!(t->lane_mask & lane_mask))
46+
continue;
47+
48+
writel(t->val, base + t->offset);
49+
}
50+
}
51+
52+
static inline void qmp_configure(void __iomem *base,
53+
const struct qmp_phy_init_tbl tbl[],
54+
int num)
55+
{
56+
qmp_configure_lane(base, tbl, num, 0xff);
57+
}
58+
59+
#endif

‎drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c‎

Lines changed: 6 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,8 @@
1919
#include <linux/reset.h>
2020
#include <linux/slab.h>
2121

22+
#include "phy-qcom-qmp-common.h"
23+
2224
#include "phy-qcom-qmp.h"
2325

2426
/* QPHY_SW_RESET bit */
@@ -39,30 +41,6 @@
3941
#define POWER_DOWN_DELAY_US_MIN 10
4042
#define POWER_DOWN_DELAY_US_MAX 20
4143

42-
struct qmp_phy_init_tbl {
43-
unsigned int offset;
44-
unsigned int val;
45-
/*
46-
* mask of lanes for which this register is written
47-
* for cases when second lane needs different values
48-
*/
49-
u8 lane_mask;
50-
};
51-
52-
#define QMP_PHY_INIT_CFG(o, v) \
53-
{ \
54-
.offset = o, \
55-
.val = v, \
56-
.lane_mask = 0xff, \
57-
}
58-
59-
#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
60-
{ \
61-
.offset = o, \
62-
.val = v, \
63-
.lane_mask = l, \
64-
}
65-
6644
/* set of registers with offsets different per-PHY */
6745
enum qphy_reg_layout {
6846
/* Common block control registers */
@@ -307,32 +285,6 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
307285
.regs = pciephy_regs_layout,
308286
};
309287

310-
static void qmp_pcie_msm8996_configure_lane(void __iomem *base,
311-
const struct qmp_phy_init_tbl tbl[],
312-
int num,
313-
u8 lane_mask)
314-
{
315-
int i;
316-
const struct qmp_phy_init_tbl *t = tbl;
317-
318-
if (!t)
319-
return;
320-
321-
for (i = 0; i < num; i++, t++) {
322-
if (!(t->lane_mask & lane_mask))
323-
continue;
324-
325-
writel(t->val, base + t->offset);
326-
}
327-
}
328-
329-
static void qmp_pcie_msm8996_configure(void __iomem *base,
330-
const struct qmp_phy_init_tbl tbl[],
331-
int num)
332-
{
333-
qmp_pcie_msm8996_configure_lane(base, tbl, num, 0xff);
334-
}
335-
336288
static int qmp_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
337289
{
338290
struct qcom_qmp *qmp = qphy->qmp;
@@ -344,7 +296,7 @@ static int qmp_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
344296
unsigned int val;
345297
int ret;
346298

347-
qmp_pcie_msm8996_configure(serdes, serdes_tbl, serdes_tbl_num);
299+
qmp_configure(serdes, serdes_tbl, serdes_tbl_num);
348300

349301
qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
350302
qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
@@ -487,9 +439,9 @@ static int qmp_pcie_msm8996_power_on(struct phy *phy)
487439
}
488440

489441
/* Tx, Rx, and PCS configurations */
490-
qmp_pcie_msm8996_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
491-
qmp_pcie_msm8996_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
492-
qmp_pcie_msm8996_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
442+
qmp_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
443+
qmp_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
444+
qmp_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
493445

494446
/*
495447
* Pull out PHY from POWER DOWN state.

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