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prabhakarladgeertu
prabhakarlad
authored and
geertu
committed
pinctrl: renesas: rzg2l: Add support for RZ/V2N SoC
Add pinctrl support for the Renesas RZ/V2N SoC by reusing the existing RZ/V2H(P) pin configuration data. The PFC block is nearly identical, with the only difference being the absence of `PCIE1_RSTOUTB` on RZ/V2N. To handle this, the rzv2h_dedicated_pins array is refactored into a common and pcie1 subset. This enables reuse of the common portion across both SoCs, while excluding PCIE1_RSTOUTB for RZ/V2N. This change allows the pinctrl-rzg2l driver to support RZ/V2N without duplicating large parts of the RZ/V2H configuration. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250415130854.242227-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
1 parent 0af2f6b commit 5488aa0

2 files changed

Lines changed: 170 additions & 130 deletions

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‎drivers/pinctrl/renesas/Kconfig‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,7 @@ config PINCTRL_RENESAS
4242
select PINCTRL_RZG2L if ARCH_RZG2L
4343
select PINCTRL_RZV2M if ARCH_R9A09G011
4444
select PINCTRL_RZG2L if ARCH_R9A09G047
45+
select PINCTRL_RZG2L if ARCH_R9A09G056
4546
select PINCTRL_RZG2L if ARCH_R9A09G057
4647
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
4748
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264

‎drivers/pinctrl/renesas/pinctrl-rzg2l.c‎

Lines changed: 169 additions & 130 deletions
Original file line numberDiff line numberDiff line change
@@ -2230,135 +2230,146 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
22302230
PIN_CFG_IO_VMC_SD1)) },
22312231
};
22322232

2233-
static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
2234-
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
2235-
{ "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2236-
PIN_CFG_IEN)) },
2237-
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2238-
{ "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2239-
PIN_CFG_PUPD | PIN_CFG_NOD)) },
2240-
{ "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2241-
PIN_CFG_PUPD | PIN_CFG_NOD)) },
2242-
{ "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2243-
PIN_CFG_PUPD)) },
2244-
{ "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2245-
PIN_CFG_PUPD)) },
2246-
{ "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2247-
PIN_CFG_PUPD | PIN_CFG_OEN)) },
2248-
{ "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2249-
PIN_CFG_PUPD | PIN_CFG_OEN)) },
2250-
{ "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2251-
PIN_CFG_PUPD | PIN_CFG_OEN)) },
2252-
{ "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2253-
PIN_CFG_PUPD)) },
2254-
{ "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2255-
PIN_CFG_PUPD | PIN_CFG_OEN)) },
2256-
{ "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) },
2257-
{ "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) },
2258-
{ "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) },
2259-
{ "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2260-
PIN_CFG_PUPD)) },
2261-
{ "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2262-
PIN_CFG_PUPD)) },
2263-
{ "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2264-
PIN_CFG_PUPD)) },
2265-
{ "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2266-
PIN_CFG_PUPD)) },
2267-
{ "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2268-
PIN_CFG_PUPD)) },
2269-
{ "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2270-
PIN_CFG_PUPD)) },
2271-
{ "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2272-
PIN_CFG_PUPD)) },
2273-
{ "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2274-
PIN_CFG_PUPD)) },
2275-
{ "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2276-
{ "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2277-
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2278-
{ "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2279-
{ "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2280-
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2281-
{ "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2282-
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2283-
{ "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2284-
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2285-
{ "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2286-
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2287-
{ "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2288-
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2289-
{ "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2290-
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2291-
{ "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2292-
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2293-
{ "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2294-
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2295-
{ "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2296-
{ "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2297-
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2298-
{ "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2299-
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2300-
{ "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2301-
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2302-
{ "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2303-
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2304-
{ "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2305-
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2306-
{ "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2307-
{ "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2308-
{ "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2309-
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2310-
{ "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2311-
PIN_CFG_PUPD)) },
2312-
{ "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) },
2313-
{ "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2314-
PIN_CFG_PUPD)) },
2315-
{ "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2316-
PIN_CFG_PUPD)) },
2317-
{ "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) },
2318-
{ "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) },
2319-
{ "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2320-
PIN_CFG_PUPD | PIN_CFG_OEN)) },
2321-
{ "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) },
2322-
{ "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) },
2323-
{ "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2324-
PIN_CFG_PUPD)) },
2325-
{ "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2326-
PIN_CFG_PUPD)) },
2327-
{ "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2328-
PIN_CFG_PUPD)) },
2329-
{ "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2330-
PIN_CFG_PUPD)) },
2331-
{ "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) },
2332-
{ "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) },
2333-
{ "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) },
2334-
{ "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) },
2335-
{ "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2336-
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2337-
{ "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2338-
PIN_CFG_PUPD)) },
2339-
{ "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) },
2340-
{ "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2233+
static const struct {
2234+
struct rzg2l_dedicated_configs common[77];
2235+
struct rzg2l_dedicated_configs pcie1[1];
2236+
} rzv2h_dedicated_pins = {
2237+
.common = {
2238+
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
2239+
{ "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2240+
PIN_CFG_IEN)) },
2241+
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2242+
{ "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2243+
PIN_CFG_PUPD | PIN_CFG_NOD)) },
2244+
{ "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2245+
PIN_CFG_PUPD | PIN_CFG_NOD)) },
2246+
{ "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2247+
PIN_CFG_PUPD)) },
2248+
{ "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2249+
PIN_CFG_PUPD)) },
2250+
{ "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2251+
PIN_CFG_PUPD | PIN_CFG_OEN)) },
2252+
{ "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2253+
PIN_CFG_PUPD | PIN_CFG_OEN)) },
2254+
{ "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2255+
PIN_CFG_PUPD | PIN_CFG_OEN)) },
2256+
{ "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2257+
PIN_CFG_PUPD)) },
2258+
{ "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2259+
PIN_CFG_PUPD | PIN_CFG_OEN)) },
2260+
{ "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) },
2261+
{ "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) },
2262+
{ "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) },
2263+
{ "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2264+
PIN_CFG_PUPD)) },
2265+
{ "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2266+
PIN_CFG_PUPD)) },
2267+
{ "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2268+
PIN_CFG_PUPD)) },
2269+
{ "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2270+
PIN_CFG_PUPD)) },
2271+
{ "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2272+
PIN_CFG_PUPD)) },
2273+
{ "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2274+
PIN_CFG_PUPD)) },
2275+
{ "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2276+
PIN_CFG_PUPD)) },
2277+
{ "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2278+
PIN_CFG_PUPD)) },
2279+
{ "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2280+
{ "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2281+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2282+
{ "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2283+
{ "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2284+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2285+
{ "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2286+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2287+
{ "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2288+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2289+
{ "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2290+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2291+
{ "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2292+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2293+
{ "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2294+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2295+
{ "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2296+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2297+
{ "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2298+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2299+
{ "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2300+
{ "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2301+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2302+
{ "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2303+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2304+
{ "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2305+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2306+
{ "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2307+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2308+
{ "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2309+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2310+
{ "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H |
2311+
PIN_CFG_SR)) },
2312+
{ "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2313+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2314+
{ "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
23412315
PIN_CFG_PUPD)) },
2342-
{ "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2343-
PIN_CFG_PUPD)) },
2344-
{ "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) },
2345-
{ "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) },
2346-
{ "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2347-
PIN_CFG_PUPD | PIN_CFG_OEN)) },
2348-
{ "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) },
2349-
{ "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) },
2350-
{ "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2351-
PIN_CFG_PUPD)) },
2352-
{ "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2353-
PIN_CFG_PUPD)) },
2354-
{ "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2355-
PIN_CFG_PUPD)) },
2356-
{ "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2357-
PIN_CFG_PUPD)) },
2358-
{ "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) },
2359-
{ "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) },
2360-
{ "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) },
2361-
{ "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
2316+
{ "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) },
2317+
{ "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H |
2318+
PIN_CFG_SR |
2319+
PIN_CFG_PUPD)) },
2320+
{ "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2321+
PIN_CFG_PUPD)) },
2322+
{ "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) },
2323+
{ "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) },
2324+
{ "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2325+
PIN_CFG_PUPD | PIN_CFG_OEN)) },
2326+
{ "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) },
2327+
{ "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) },
2328+
{ "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2329+
PIN_CFG_PUPD)) },
2330+
{ "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2331+
PIN_CFG_PUPD)) },
2332+
{ "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2333+
PIN_CFG_PUPD)) },
2334+
{ "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2335+
PIN_CFG_PUPD)) },
2336+
{ "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) },
2337+
{ "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) },
2338+
{ "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) },
2339+
{ "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) },
2340+
{ "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2341+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
2342+
{ "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2343+
PIN_CFG_PUPD)) },
2344+
{ "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) },
2345+
{ "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H |
2346+
PIN_CFG_SR |
2347+
PIN_CFG_PUPD)) },
2348+
{ "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2349+
PIN_CFG_PUPD)) },
2350+
{ "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) },
2351+
{ "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) },
2352+
{ "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2353+
PIN_CFG_PUPD | PIN_CFG_OEN)) },
2354+
{ "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) },
2355+
{ "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) },
2356+
{ "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2357+
PIN_CFG_PUPD)) },
2358+
{ "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2359+
PIN_CFG_PUPD)) },
2360+
{ "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2361+
PIN_CFG_PUPD)) },
2362+
{ "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2363+
PIN_CFG_PUPD)) },
2364+
{ "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) },
2365+
{ "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) },
2366+
{ "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) },
2367+
{ "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
2368+
},
2369+
.pcie1 = {
2370+
{ "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H |
2371+
PIN_CFG_SR)) },
2372+
},
23622373
};
23632374

23642375
static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = {
@@ -3349,13 +3360,37 @@ static struct rzg2l_pinctrl_data r9a09g047_data = {
33493360
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
33503361
};
33513362

3363+
static struct rzg2l_pinctrl_data r9a09g056_data = {
3364+
.port_pins = rzv2h_gpio_names,
3365+
.port_pin_configs = r9a09g057_gpio_configs,
3366+
.n_ports = ARRAY_SIZE(r9a09g057_gpio_configs),
3367+
.dedicated_pins = rzv2h_dedicated_pins.common,
3368+
.n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT,
3369+
.n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common),
3370+
.hwcfg = &rzv2h_hwcfg,
3371+
.variable_pin_cfg = r9a09g057_variable_pin_cfg,
3372+
.n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg),
3373+
.num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
3374+
.custom_params = renesas_rzv2h_custom_bindings,
3375+
#ifdef CONFIG_DEBUG_FS
3376+
.custom_conf_items = renesas_rzv2h_conf_items,
3377+
#endif
3378+
.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
3379+
.pmc_writeb = &rzv2h_pmc_writeb,
3380+
.oen_read = &rzv2h_oen_read,
3381+
.oen_write = &rzv2h_oen_write,
3382+
.hw_to_bias_param = &rzv2h_hw_to_bias_param,
3383+
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
3384+
};
3385+
33523386
static struct rzg2l_pinctrl_data r9a09g057_data = {
33533387
.port_pins = rzv2h_gpio_names,
33543388
.port_pin_configs = r9a09g057_gpio_configs,
33553389
.n_ports = ARRAY_SIZE(r9a09g057_gpio_configs),
3356-
.dedicated_pins = rzv2h_dedicated_pins,
3390+
.dedicated_pins = rzv2h_dedicated_pins.common,
33573391
.n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT,
3358-
.n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins),
3392+
.n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common) +
3393+
ARRAY_SIZE(rzv2h_dedicated_pins.pcie1),
33593394
.hwcfg = &rzv2h_hwcfg,
33603395
.variable_pin_cfg = r9a09g057_variable_pin_cfg,
33613396
.n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg),
@@ -3389,6 +3424,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = {
33893424
.compatible = "renesas,r9a09g047-pinctrl",
33903425
.data = &r9a09g047_data,
33913426
},
3427+
{
3428+
.compatible = "renesas,r9a09g056-pinctrl",
3429+
.data = &r9a09g056_data,
3430+
},
33923431
{
33933432
.compatible = "renesas,r9a09g057-pinctrl",
33943433
.data = &r9a09g057_data,

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