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Roy-CW.Yehmbgg
Roy-CW.Yeh
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soc: mediatek: mutex: support MT8195 VPPSYS
Add MT8195 VPPSYS0 and VPPSYS1 mutex info to driver data Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Change-Id: Ie371dc9dcf35ea308d9460acd60fb9c3d6475deb Link: https://lore.kernel.org/r/20230206091109.1324-7-moudy.ho@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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‎drivers/soc/mediatek/mtk-mutex.c‎

Lines changed: 102 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -164,6 +164,53 @@
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#define MT8195_MUTEX_MOD_DISP1_DPI1 26
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#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 27
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/* VPPSYS0 */
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#define MT8195_MUTEX_MOD_MDP_RDMA0 0
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#define MT8195_MUTEX_MOD_MDP_FG0 1
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#define MT8195_MUTEX_MOD_MDP_STITCH0 2
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#define MT8195_MUTEX_MOD_MDP_HDR0 3
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#define MT8195_MUTEX_MOD_MDP_AAL0 4
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#define MT8195_MUTEX_MOD_MDP_RSZ0 5
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#define MT8195_MUTEX_MOD_MDP_TDSHP0 6
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#define MT8195_MUTEX_MOD_MDP_COLOR0 7
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#define MT8195_MUTEX_MOD_MDP_OVL0 8
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#define MT8195_MUTEX_MOD_MDP_PAD0 9
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#define MT8195_MUTEX_MOD_MDP_TCC0 10
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#define MT8195_MUTEX_MOD_MDP_WROT0 11
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/* VPPSYS1 */
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#define MT8195_MUTEX_MOD_MDP_TCC1 3
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#define MT8195_MUTEX_MOD_MDP_RDMA1 4
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#define MT8195_MUTEX_MOD_MDP_RDMA2 5
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#define MT8195_MUTEX_MOD_MDP_RDMA3 6
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#define MT8195_MUTEX_MOD_MDP_FG1 7
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#define MT8195_MUTEX_MOD_MDP_FG2 8
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#define MT8195_MUTEX_MOD_MDP_FG3 9
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#define MT8195_MUTEX_MOD_MDP_HDR1 10
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#define MT8195_MUTEX_MOD_MDP_HDR2 11
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#define MT8195_MUTEX_MOD_MDP_HDR3 12
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#define MT8195_MUTEX_MOD_MDP_AAL1 13
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#define MT8195_MUTEX_MOD_MDP_AAL2 14
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#define MT8195_MUTEX_MOD_MDP_AAL3 15
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#define MT8195_MUTEX_MOD_MDP_RSZ1 16
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#define MT8195_MUTEX_MOD_MDP_RSZ2 17
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#define MT8195_MUTEX_MOD_MDP_RSZ3 18
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#define MT8195_MUTEX_MOD_MDP_TDSHP1 19
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#define MT8195_MUTEX_MOD_MDP_TDSHP2 20
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#define MT8195_MUTEX_MOD_MDP_TDSHP3 21
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#define MT8195_MUTEX_MOD_MDP_MERGE2 22
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#define MT8195_MUTEX_MOD_MDP_MERGE3 23
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#define MT8195_MUTEX_MOD_MDP_COLOR1 24
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#define MT8195_MUTEX_MOD_MDP_COLOR2 25
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#define MT8195_MUTEX_MOD_MDP_COLOR3 26
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#define MT8195_MUTEX_MOD_MDP_OVL1 27
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#define MT8195_MUTEX_MOD_MDP_PAD1 28
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#define MT8195_MUTEX_MOD_MDP_PAD2 29
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#define MT8195_MUTEX_MOD_MDP_PAD3 30
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#define MT8195_MUTEX_MOD_MDP_WROT1 31
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#define MT8195_MUTEX_MOD_MDP_WROT2 32
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#define MT8195_MUTEX_MOD_MDP_WROT3 33
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#define MT8365_MUTEX_MOD_DISP_OVL0 7
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#define MT8365_MUTEX_MOD_DISP_OVL0_2L 8
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#define MT8365_MUTEX_MOD_DISP_RDMA0 9
@@ -444,6 +491,52 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
444491
[DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
445492
};
446493

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static const unsigned int mt8195_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
495+
[MUTEX_MOD_IDX_MDP_RDMA0] = MT8195_MUTEX_MOD_MDP_RDMA0,
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[MUTEX_MOD_IDX_MDP_RDMA1] = MT8195_MUTEX_MOD_MDP_RDMA1,
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[MUTEX_MOD_IDX_MDP_RDMA2] = MT8195_MUTEX_MOD_MDP_RDMA2,
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[MUTEX_MOD_IDX_MDP_RDMA3] = MT8195_MUTEX_MOD_MDP_RDMA3,
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[MUTEX_MOD_IDX_MDP_STITCH0] = MT8195_MUTEX_MOD_MDP_STITCH0,
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[MUTEX_MOD_IDX_MDP_FG0] = MT8195_MUTEX_MOD_MDP_FG0,
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[MUTEX_MOD_IDX_MDP_FG1] = MT8195_MUTEX_MOD_MDP_FG1,
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[MUTEX_MOD_IDX_MDP_FG2] = MT8195_MUTEX_MOD_MDP_FG2,
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[MUTEX_MOD_IDX_MDP_FG3] = MT8195_MUTEX_MOD_MDP_FG3,
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[MUTEX_MOD_IDX_MDP_HDR0] = MT8195_MUTEX_MOD_MDP_HDR0,
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[MUTEX_MOD_IDX_MDP_HDR1] = MT8195_MUTEX_MOD_MDP_HDR1,
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[MUTEX_MOD_IDX_MDP_HDR2] = MT8195_MUTEX_MOD_MDP_HDR2,
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[MUTEX_MOD_IDX_MDP_HDR3] = MT8195_MUTEX_MOD_MDP_HDR3,
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[MUTEX_MOD_IDX_MDP_AAL0] = MT8195_MUTEX_MOD_MDP_AAL0,
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[MUTEX_MOD_IDX_MDP_AAL1] = MT8195_MUTEX_MOD_MDP_AAL1,
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[MUTEX_MOD_IDX_MDP_AAL2] = MT8195_MUTEX_MOD_MDP_AAL2,
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[MUTEX_MOD_IDX_MDP_AAL3] = MT8195_MUTEX_MOD_MDP_AAL3,
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[MUTEX_MOD_IDX_MDP_RSZ0] = MT8195_MUTEX_MOD_MDP_RSZ0,
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[MUTEX_MOD_IDX_MDP_RSZ1] = MT8195_MUTEX_MOD_MDP_RSZ1,
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[MUTEX_MOD_IDX_MDP_RSZ2] = MT8195_MUTEX_MOD_MDP_RSZ2,
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[MUTEX_MOD_IDX_MDP_RSZ3] = MT8195_MUTEX_MOD_MDP_RSZ3,
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[MUTEX_MOD_IDX_MDP_MERGE2] = MT8195_MUTEX_MOD_MDP_MERGE2,
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[MUTEX_MOD_IDX_MDP_MERGE3] = MT8195_MUTEX_MOD_MDP_MERGE3,
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[MUTEX_MOD_IDX_MDP_TDSHP0] = MT8195_MUTEX_MOD_MDP_TDSHP0,
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[MUTEX_MOD_IDX_MDP_TDSHP1] = MT8195_MUTEX_MOD_MDP_TDSHP1,
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[MUTEX_MOD_IDX_MDP_TDSHP2] = MT8195_MUTEX_MOD_MDP_TDSHP2,
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[MUTEX_MOD_IDX_MDP_TDSHP3] = MT8195_MUTEX_MOD_MDP_TDSHP3,
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[MUTEX_MOD_IDX_MDP_COLOR0] = MT8195_MUTEX_MOD_MDP_COLOR0,
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[MUTEX_MOD_IDX_MDP_COLOR1] = MT8195_MUTEX_MOD_MDP_COLOR1,
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[MUTEX_MOD_IDX_MDP_COLOR2] = MT8195_MUTEX_MOD_MDP_COLOR2,
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[MUTEX_MOD_IDX_MDP_COLOR3] = MT8195_MUTEX_MOD_MDP_COLOR3,
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[MUTEX_MOD_IDX_MDP_OVL0] = MT8195_MUTEX_MOD_MDP_OVL0,
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[MUTEX_MOD_IDX_MDP_OVL1] = MT8195_MUTEX_MOD_MDP_OVL1,
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[MUTEX_MOD_IDX_MDP_PAD0] = MT8195_MUTEX_MOD_MDP_PAD0,
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[MUTEX_MOD_IDX_MDP_PAD1] = MT8195_MUTEX_MOD_MDP_PAD1,
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[MUTEX_MOD_IDX_MDP_PAD2] = MT8195_MUTEX_MOD_MDP_PAD2,
531+
[MUTEX_MOD_IDX_MDP_PAD3] = MT8195_MUTEX_MOD_MDP_PAD3,
532+
[MUTEX_MOD_IDX_MDP_TCC0] = MT8195_MUTEX_MOD_MDP_TCC0,
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[MUTEX_MOD_IDX_MDP_TCC1] = MT8195_MUTEX_MOD_MDP_TCC1,
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[MUTEX_MOD_IDX_MDP_WROT0] = MT8195_MUTEX_MOD_MDP_WROT0,
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[MUTEX_MOD_IDX_MDP_WROT1] = MT8195_MUTEX_MOD_MDP_WROT1,
536+
[MUTEX_MOD_IDX_MDP_WROT2] = MT8195_MUTEX_MOD_MDP_WROT2,
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[MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3,
538+
};
539+
447540
static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = {
448541
[DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL,
449542
[DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR,
@@ -604,6 +697,13 @@ static const struct mtk_mutex_data mt8195_mutex_driver_data = {
604697
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
605698
};
606699

700+
static const struct mtk_mutex_data mt8195_vpp_mutex_driver_data = {
701+
.mutex_sof = mt8195_mutex_sof,
702+
.mutex_mod_reg = MT8183_MUTEX0_MOD0,
703+
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
704+
.mutex_table_mod = mt8195_mutex_table_mod,
705+
};
706+
607707
static const struct mtk_mutex_data mt8365_mutex_driver_data = {
608708
.mutex_mod = mt8365_mutex_mod,
609709
.mutex_sof = mt8183_mutex_sof,
@@ -962,6 +1062,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
9621062
.data = &mt8192_mutex_driver_data},
9631063
{ .compatible = "mediatek,mt8195-disp-mutex",
9641064
.data = &mt8195_mutex_driver_data},
1065+
{ .compatible = "mediatek,mt8195-vpp-mutex",
1066+
.data = &mt8195_vpp_mutex_driver_data},
9651067
{ .compatible = "mediatek,mt8365-disp-mutex",
9661068
.data = &mt8365_mutex_driver_data},
9671069
{},

‎include/linux/soc/mediatek/mtk-mutex.h‎

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,41 @@ enum mtk_mutex_mod_index {
2222
MUTEX_MOD_IDX_MDP_CCORR0,
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MUTEX_MOD_IDX_MDP_HDR0,
2424
MUTEX_MOD_IDX_MDP_COLOR0,
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MUTEX_MOD_IDX_MDP_RDMA1,
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MUTEX_MOD_IDX_MDP_RDMA2,
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MUTEX_MOD_IDX_MDP_RDMA3,
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MUTEX_MOD_IDX_MDP_STITCH0,
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MUTEX_MOD_IDX_MDP_FG0,
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MUTEX_MOD_IDX_MDP_FG1,
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MUTEX_MOD_IDX_MDP_FG2,
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MUTEX_MOD_IDX_MDP_FG3,
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MUTEX_MOD_IDX_MDP_HDR1,
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MUTEX_MOD_IDX_MDP_HDR2,
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MUTEX_MOD_IDX_MDP_HDR3,
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MUTEX_MOD_IDX_MDP_AAL1,
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MUTEX_MOD_IDX_MDP_AAL2,
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MUTEX_MOD_IDX_MDP_AAL3,
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MUTEX_MOD_IDX_MDP_RSZ2,
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MUTEX_MOD_IDX_MDP_RSZ3,
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MUTEX_MOD_IDX_MDP_MERGE2,
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MUTEX_MOD_IDX_MDP_MERGE3,
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MUTEX_MOD_IDX_MDP_TDSHP1,
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MUTEX_MOD_IDX_MDP_TDSHP2,
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MUTEX_MOD_IDX_MDP_TDSHP3,
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MUTEX_MOD_IDX_MDP_COLOR1,
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MUTEX_MOD_IDX_MDP_COLOR2,
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MUTEX_MOD_IDX_MDP_COLOR3,
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MUTEX_MOD_IDX_MDP_OVL0,
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MUTEX_MOD_IDX_MDP_OVL1,
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MUTEX_MOD_IDX_MDP_PAD0,
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MUTEX_MOD_IDX_MDP_PAD1,
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MUTEX_MOD_IDX_MDP_PAD2,
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MUTEX_MOD_IDX_MDP_PAD3,
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MUTEX_MOD_IDX_MDP_TCC0,
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MUTEX_MOD_IDX_MDP_TCC1,
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MUTEX_MOD_IDX_MDP_WROT1,
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MUTEX_MOD_IDX_MDP_WROT2,
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MUTEX_MOD_IDX_MDP_WROT3,
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MUTEX_MOD_IDX_MAX /* ALWAYS keep at the end */
2762
};

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