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riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
Add a minimal device tree for StarFive JH7110 VisionFive 2 board which has version A and version B. Support booting and basic clock/reset/pinctrl/uart drivers. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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‎arch/riscv/boot/dts/starfive/Makefile‎

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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb

‎arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts‎

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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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*/
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/dts-v1/;
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#include "jh7110-starfive-visionfive-2.dtsi"
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/ {
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model = "StarFive VisionFive 2 v1.2A";
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compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
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};

‎arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts‎

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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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*/
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/dts-v1/;
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#include "jh7110-starfive-visionfive-2.dtsi"
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/ {
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model = "StarFive VisionFive 2 v1.3B";
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compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
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};

‎arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi‎

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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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*/
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/dts-v1/;
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#include "jh7110.dtsi"
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#include "jh7110-pinfunc.h"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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aliases {
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i2c0 = &i2c0;
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i2c2 = &i2c2;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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cpus {
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timebase-frequency = <4000000>;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0x1 0x0>;
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};
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
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priority = <224>;
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};
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};
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&gmac0_rgmii_rxin {
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clock-frequency = <125000000>;
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};
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&gmac0_rmii_refin {
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clock-frequency = <50000000>;
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};
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&gmac1_rgmii_rxin {
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clock-frequency = <125000000>;
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};
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&gmac1_rmii_refin {
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clock-frequency = <50000000>;
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};
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&i2srx_bclk_ext {
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clock-frequency = <12288000>;
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};
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&i2srx_lrck_ext {
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clock-frequency = <192000>;
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};
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&i2stx_bclk_ext {
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clock-frequency = <12288000>;
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};
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&i2stx_lrck_ext {
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clock-frequency = <192000>;
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};
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&mclk_ext {
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clock-frequency = <12288000>;
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};
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&osc {
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clock-frequency = <24000000>;
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};
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&rtc_osc {
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clock-frequency = <32768>;
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};
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&tdm_ext {
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clock-frequency = <49152000>;
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};
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&i2c0 {
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clock-frequency = <100000>;
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i2c-sda-hold-time-ns = <300>;
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i2c-sda-falling-time-ns = <510>;
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i2c-scl-falling-time-ns = <510>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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};
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&i2c2 {
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clock-frequency = <100000>;
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i2c-sda-hold-time-ns = <300>;
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i2c-sda-falling-time-ns = <510>;
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i2c-scl-falling-time-ns = <510>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_pins>;
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status = "okay";
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};
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&i2c5 {
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clock-frequency = <100000>;
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i2c-sda-hold-time-ns = <300>;
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i2c-sda-falling-time-ns = <510>;
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i2c-scl-falling-time-ns = <510>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_pins>;
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status = "okay";
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};
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&i2c6 {
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clock-frequency = <100000>;
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i2c-sda-hold-time-ns = <300>;
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i2c-sda-falling-time-ns = <510>;
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i2c-scl-falling-time-ns = <510>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c6_pins>;
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status = "okay";
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};
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&sysgpio {
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i2c0_pins: i2c0-0 {
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i2c-pins {
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pinmux = <GPIOMUX(57, GPOUT_LOW,
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GPOEN_SYS_I2C0_CLK,
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GPI_SYS_I2C0_CLK)>,
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<GPIOMUX(58, GPOUT_LOW,
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GPOEN_SYS_I2C0_DATA,
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GPI_SYS_I2C0_DATA)>;
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bias-disable; /* external pull-up */
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input-enable;
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input-schmitt-enable;
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};
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};
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i2c2_pins: i2c2-0 {
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i2c-pins {
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pinmux = <GPIOMUX(3, GPOUT_LOW,
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GPOEN_SYS_I2C2_CLK,
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GPI_SYS_I2C2_CLK)>,
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<GPIOMUX(2, GPOUT_LOW,
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GPOEN_SYS_I2C2_DATA,
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GPI_SYS_I2C2_DATA)>;
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bias-disable; /* external pull-up */
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input-enable;
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input-schmitt-enable;
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};
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};
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i2c5_pins: i2c5-0 {
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i2c-pins {
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pinmux = <GPIOMUX(19, GPOUT_LOW,
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GPOEN_SYS_I2C5_CLK,
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GPI_SYS_I2C5_CLK)>,
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<GPIOMUX(20, GPOUT_LOW,
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GPOEN_SYS_I2C5_DATA,
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GPI_SYS_I2C5_DATA)>;
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bias-disable; /* external pull-up */
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input-enable;
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input-schmitt-enable;
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};
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};
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i2c6_pins: i2c6-0 {
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i2c-pins {
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pinmux = <GPIOMUX(16, GPOUT_LOW,
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GPOEN_SYS_I2C6_CLK,
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GPI_SYS_I2C6_CLK)>,
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<GPIOMUX(17, GPOUT_LOW,
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GPOEN_SYS_I2C6_DATA,
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GPI_SYS_I2C6_DATA)>;
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bias-disable; /* external pull-up */
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input-enable;
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input-schmitt-enable;
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};
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};
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uart0_pins: uart0-0 {
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tx-pins {
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pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
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GPOEN_ENABLE,
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GPI_NONE)>;
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bias-disable;
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drive-strength = <12>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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rx-pins {
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pinmux = <GPIOMUX(6, GPOUT_LOW,
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GPOEN_DISABLE,
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GPI_SYS_UART0_RX)>;
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bias-disable; /* external pull-up */
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drive-strength = <2>;
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input-enable;
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input-schmitt-enable;
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slew-rate = <0>;
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};
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};

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