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andy-shevlag-linaro
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mfd: lpc_ich: Switch to generic p2sb_bar()
Instead of open coding p2sb_bar() functionality we are going to use generic library. There is one more user en route. This is more than just a clean-up. It also fixes a potential issue seen when SPI BAR is 64-bit. The current code works if and only if the PCI BAR of the hidden device is inside 4G address space. In case when firmware decides to go above 4G, we will get a wrong address. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Henning Schild <henning.schild@siemens.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee@kernel.org>
1 parent 6e3b29d commit 5597931

2 files changed

Lines changed: 9 additions & 19 deletions

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drivers/mfd/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -572,6 +572,7 @@ config LPC_ICH
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tristate "Intel ICH LPC"
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depends on PCI
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select MFD_CORE
575+
select P2SB if X86
575576
help
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The LPC bridge function of the Intel ICH provides support for
577578
many functional units. This driver provides needed support for

drivers/mfd/lpc_ich.c

Lines changed: 8 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,7 @@
4545
#include <linux/mfd/core.h>
4646
#include <linux/mfd/lpc_ich.h>
4747
#include <linux/platform_data/itco_wdt.h>
48+
#include <linux/platform_data/x86/p2sb.h>
4849

4950
#define ACPIBASE 0x40
5051
#define ACPIBASE_GPE_OFF 0x28
@@ -71,8 +72,6 @@
7172
#define BCR 0xdc
7273
#define BCR_WPD BIT(0)
7374

74-
#define SPIBASE_APL_SZ 4096
75-
7675
#define GPIOBASE_ICH0 0x58
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#define GPIOCTRL_ICH0 0x5C
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#define GPIOBASE_ICH6 0x48
@@ -1134,6 +1133,7 @@ static int lpc_ich_init_spi(struct pci_dev *dev)
11341133
struct resource *res = &intel_spi_res[0];
11351134
struct intel_spi_boardinfo *info;
11361135
u32 spi_base, rcba;
1136+
int ret;
11371137

11381138
info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
11391139
if (!info)
@@ -1164,30 +1164,19 @@ static int lpc_ich_init_spi(struct pci_dev *dev)
11641164
}
11651165
break;
11661166

1167-
case INTEL_SPI_BXT: {
1168-
unsigned int p2sb = PCI_DEVFN(13, 0);
1169-
unsigned int spi = PCI_DEVFN(13, 2);
1170-
struct pci_bus *bus = dev->bus;
1171-
1167+
case INTEL_SPI_BXT:
11721168
/*
11731169
* The P2SB is hidden by BIOS and we need to unhide it in
11741170
* order to read BAR of the SPI flash device. Once that is
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* done we hide it again.
11761172
*/
1177-
pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0);
1178-
pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0,
1179-
&spi_base);
1180-
if (spi_base != ~0) {
1181-
res->start = spi_base & 0xfffffff0;
1182-
res->end = res->start + SPIBASE_APL_SZ - 1;
1183-
1184-
info->set_writeable = lpc_ich_bxt_set_writeable;
1185-
info->data = dev;
1186-
}
1173+
ret = p2sb_bar(dev->bus, PCI_DEVFN(13, 2), res);
1174+
if (ret)
1175+
return ret;
11871176

1188-
pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1);
1177+
info->set_writeable = lpc_ich_bxt_set_writeable;
1178+
info->data = dev;
11891179
break;
1190-
}
11911180

11921181
default:
11931182
return -EINVAL;

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