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MIPS: Ingenic: Refresh device tree for Ingenic SoCs and boards.
1.Add SSI nodes for X1000 SoC and X1830 SoC from Ingenic. 2.Refresh SSI related nodes in CU1000-Neo and CU1830-Neo. 3.The X1830 SoC used by the CU1830-Neo and the X1000 SoC used by the CU1000-Neo are both single-core processors, therefore the "OST_CLK_PERCPU_TIMER" ABI should not be used in the OST nodes of the CU1830-Neo and CU1000-Neo, it is just a coincidence that there is no problem now. So replace the misused "OST_CLK_PERCPU_TIMER" ABI with the correct "OST_CLK_EVENT_TIMER" ABI. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
1 parent b2a5df7 commit 562dc4c

4 files changed

Lines changed: 138 additions & 74 deletions

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‎arch/mips/boot/dts/ingenic/cu1000-neo.dts‎

Lines changed: 40 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -31,42 +31,6 @@
3131
};
3232
};
3333

34-
ssi: spi-gpio {
35-
compatible = "spi-gpio";
36-
#address-cells = <1>;
37-
#size-cells = <0>;
38-
num-chipselects = <1>;
39-
40-
mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
41-
miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
42-
sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
43-
cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
44-
45-
status = "okay";
46-
47-
spi-max-frequency = <50000000>;
48-
49-
sc16is752: expander@0 {
50-
compatible = "nxp,sc16is752";
51-
reg = <0>; /* CE0 */
52-
spi-max-frequency = <4000000>;
53-
54-
clocks = <&exclk_sc16is752>;
55-
56-
interrupt-parent = <&gpc>;
57-
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
58-
59-
gpio-controller;
60-
#gpio-cells = <2>;
61-
62-
exclk_sc16is752: sc16is752 {
63-
compatible = "fixed-clock";
64-
#clock-cells = <0>;
65-
clock-frequency = <48000000>;
66-
};
67-
};
68-
};
69-
7034
wlan_pwrseq: msc1-pwrseq {
7135
compatible = "mmc-pwrseq-simple";
7236

@@ -90,7 +54,7 @@
9054

9155
&ost {
9256
/* 1500 kHz for the system timer and clocksource */
93-
assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
57+
assigned-clocks = <&ost OST_CLK_EVENT_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
9458
assigned-clock-rates = <1500000>, <1500000>;
9559
};
9660

@@ -101,6 +65,39 @@
10165
pinctrl-0 = <&pins_uart2>;
10266
};
10367

68+
&ssi {
69+
status = "okay";
70+
71+
num-cs = <2>;
72+
cs-gpios = <0>, <&gpc 20 GPIO_ACTIVE_LOW>;
73+
74+
pinctrl-names = "default";
75+
pinctrl-0 = <&pins_ssi>;
76+
77+
sc16is752: expander@0 {
78+
compatible = "nxp,sc16is752";
79+
reg = <0>; /* CE0 */
80+
81+
spi-rx-bus-width = <1>;
82+
spi-tx-bus-width = <1>;
83+
spi-max-frequency = <4000000>;
84+
85+
clocks = <&exclk_sc16is752>;
86+
87+
interrupt-parent = <&gpc>;
88+
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
89+
90+
gpio-controller;
91+
#gpio-cells = <2>;
92+
93+
exclk_sc16is752: sc16is752 {
94+
compatible = "fixed-clock";
95+
#clock-cells = <0>;
96+
clock-frequency = <48000000>;
97+
};
98+
};
99+
};
100+
104101
&i2c0 {
105102
status = "okay";
106103

@@ -192,6 +189,12 @@
192189
bias-pull-up;
193190
};
194191

192+
pins_ssi: ssi {
193+
function = "ssi";
194+
groups = "ssi-dt-d", "ssi-dr-d", "ssi-clk-d", "ssi-ce0-d";
195+
bias-disable;
196+
};
197+
195198
pins_i2c0: i2c0 {
196199
function = "i2c0";
197200
groups = "i2c0-data";

‎arch/mips/boot/dts/ingenic/cu1830-neo.dts‎

Lines changed: 39 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -31,42 +31,6 @@
3131
};
3232
};
3333

34-
ssi0: spi-gpio {
35-
compatible = "spi-gpio";
36-
#address-cells = <1>;
37-
#size-cells = <0>;
38-
num-chipselects = <1>;
39-
40-
mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
41-
miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
42-
sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
43-
cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
44-
45-
status = "okay";
46-
47-
spi-max-frequency = <50000000>;
48-
49-
sc16is752: expander@0 {
50-
compatible = "nxp,sc16is752";
51-
reg = <0>; /* CE0 */
52-
spi-max-frequency = <4000000>;
53-
54-
clocks = <&exclk_sc16is752>;
55-
56-
interrupt-parent = <&gpb>;
57-
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
58-
59-
gpio-controller;
60-
#gpio-cells = <2>;
61-
62-
exclk_sc16is752: sc16is752 {
63-
compatible = "fixed-clock";
64-
#clock-cells = <0>;
65-
clock-frequency = <48000000>;
66-
};
67-
};
68-
};
69-
7034
wlan_pwrseq: msc1-pwrseq {
7135
compatible = "mmc-pwrseq-simple";
7236

@@ -90,7 +54,7 @@
9054

9155
&ost {
9256
/* 1500 kHz for the system timer and clocksource */
93-
assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
57+
assigned-clocks = <&ost OST_CLK_EVENT_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
9458
assigned-clock-rates = <1500000>, <1500000>;
9559
};
9660

@@ -101,6 +65,38 @@
10165
pinctrl-0 = <&pins_uart1>;
10266
};
10367

68+
&ssi0 {
69+
status = "okay";
70+
71+
num-cs = <2>;
72+
73+
pinctrl-names = "default";
74+
pinctrl-0 = <&pins_ssi0>;
75+
76+
sc16is752: expander@0 {
77+
compatible = "nxp,sc16is752";
78+
reg = <0>; /* CE0 */
79+
80+
spi-rx-bus-width = <1>;
81+
spi-tx-bus-width = <1>;
82+
spi-max-frequency = <4000000>;
83+
84+
clocks = <&exclk_sc16is752>;
85+
86+
interrupt-parent = <&gpb>;
87+
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
88+
89+
gpio-controller;
90+
#gpio-cells = <2>;
91+
92+
exclk_sc16is752: sc16is752 {
93+
compatible = "fixed-clock";
94+
#clock-cells = <0>;
95+
clock-frequency = <48000000>;
96+
};
97+
};
98+
};
99+
104100
&i2c0 {
105101
status = "okay";
106102

@@ -196,6 +192,12 @@
196192
bias-pull-up;
197193
};
198194

195+
pins_ssi0: ssi0 {
196+
function = "ssi0";
197+
groups = "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-ce0", "ssi0-ce1";
198+
bias-disable;
199+
};
200+
199201
pins_i2c0: i2c0 {
200202
function = "i2c0";
201203
groups = "i2c0-data";

‎arch/mips/boot/dts/ingenic/x1000.dtsi‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -258,6 +258,25 @@
258258
status = "disabled";
259259
};
260260

261+
ssi: spi@10043000 {
262+
compatible = "ingenic,x1000-spi";
263+
reg = <0x10043000 0x20>;
264+
#address-cells = <1>;
265+
#size-cells = <0>;
266+
267+
interrupt-parent = <&intc>;
268+
interrupts = <8>;
269+
270+
clocks = <&cgu X1000_CLK_SSI>;
271+
clock-names = "spi";
272+
273+
dmas = <&pdma X1000_DMA_SSI0_RX 0xffffffff>,
274+
<&pdma X1000_DMA_SSI0_TX 0xffffffff>;
275+
dma-names = "rx", "tx";
276+
277+
status = "disabled";
278+
};
279+
261280
i2c0: i2c-controller@10050000 {
262281
compatible = "ingenic,x1000-i2c";
263282
reg = <0x10050000 0x1000>;
@@ -303,6 +322,7 @@
303322
pdma: dma-controller@13420000 {
304323
compatible = "ingenic,x1000-dma";
305324
reg = <0x13420000 0x400>, <0x13421000 0x40>;
325+
306326
#dma-cells = <2>;
307327

308328
interrupt-parent = <&intc>;

‎arch/mips/boot/dts/ingenic/x1830.dtsi‎

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -240,6 +240,44 @@
240240
status = "disabled";
241241
};
242242

243+
ssi0: spi@10043000 {
244+
compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
245+
reg = <0x10043000 0x20>;
246+
#address-cells = <1>;
247+
#size-cells = <0>;
248+
249+
interrupt-parent = <&intc>;
250+
interrupts = <9>;
251+
252+
clocks = <&cgu X1830_CLK_SSI0>;
253+
clock-names = "spi";
254+
255+
dmas = <&pdma X1830_DMA_SSI0_RX 0xffffffff>,
256+
<&pdma X1830_DMA_SSI0_TX 0xffffffff>;
257+
dma-names = "rx", "tx";
258+
259+
status = "disabled";
260+
};
261+
262+
ssi1: spi@10044000 {
263+
compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
264+
reg = <0x10044000 0x20>;
265+
#address-cells = <1>;
266+
#size-cells = <0>;
267+
268+
interrupt-parent = <&intc>;
269+
interrupts = <8>;
270+
271+
clocks = <&cgu X1830_CLK_SSI1>;
272+
clock-names = "spi";
273+
274+
dmas = <&pdma X1830_DMA_SSI1_RX 0xffffffff>,
275+
<&pdma X1830_DMA_SSI1_TX 0xffffffff>;
276+
dma-names = "rx", "tx";
277+
278+
status = "disabled";
279+
};
280+
243281
i2c0: i2c-controller@10050000 {
244282
compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
245283
reg = <0x10050000 0x1000>;
@@ -294,6 +332,7 @@
294332
pdma: dma-controller@13420000 {
295333
compatible = "ingenic,x1830-dma";
296334
reg = <0x13420000 0x400>, <0x13421000 0x40>;
335+
297336
#dma-cells = <2>;
298337

299338
interrupt-parent = <&intc>;

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