clk: renesas: rcar-gen4: Add support for clock dividers in FRQCRB

The FRQCRB register on R-Car V3U, V4H and V4M do in addition to the
already supported KICK bit contain settings for the frequency division
ratios for the clocks ZTR, ZT, ZS and ZG. It is however not possible to
use the latter when registering a Z clock with the DEF_GEN4_Z() macro.

This change adds support for that by extending the existing practice of
treating the bit field offsets at multiples of 32 to map to a different
register. With this new mapping in palace

    bit offsets  0 - 31 map to FRQCRC0
    bit offsets 32 - 63 map to FRQCRC1
    bit offsets 64 - 95 map to FRQCRB

The change also adds an error condition to return an error if an unknown
offset is used.

The KICK bit defined in FRQCRB and already supported covers all three
registers and no addition to how it is handled are needed.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251106211604.2766465-3-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Author: Niklas Söderlund

drivers/clk/renesas/rcar-gen4-cpg.c

@@ -257,7 +257,7 @@ static struct clk * __init cpg_pll_clk_register(const char *name,
 }
 
 /*
- * Z0 Clock & Z1 Clock
+ * Z0, Z1 and ZG Clock
  */
 #define CPG_FRQCRB			0x00000804
 #define CPG_FRQCRB_KICK			BIT(31)
@@ -389,9 +389,14 @@ static struct clk * __init cpg_z_clk_register(const char *name,
 
 	if (offset < 32) {
 		zclk->reg = reg + CPG_FRQCRC0;
-	} else {
+	} else if (offset < 64) {
 		zclk->reg = reg + CPG_FRQCRC1;
 		offset -= 32;
+	} else if (offset < 96) {
+		zclk->reg = reg + CPG_FRQCRB;
+		offset -= 64;
+	} else {
+		return ERR_PTR(-EINVAL);
 	}
 	zclk->kick_reg = reg + CPG_FRQCRB;
 	zclk->hw.init = &init;