Skip to content

Commit 574d0f2

Browse files
ivoszbgkrzk
ivoszbg
authored and
krzk
committed
pinctrl: samsung: add exynos2200 SoC pinctrl configuration
Add support for the pin-controller found on the Exynos2200 SoC used in Samsung Galaxy S22, S22 Plus and S22 Ultra phones. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20250215113248.159386-4-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
1 parent bbdb937 commit 574d0f2

3 files changed

Lines changed: 171 additions & 0 deletions

File tree

‎drivers/pinctrl/samsung/pinctrl-exynos-arm64.c‎

Lines changed: 168 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,174 @@ static const struct samsung_pin_bank_type exynos8895_bank_type_off = {
7070
/* Pad retention control code for accessing PMU regmap */
7171
static atomic_t exynos_shared_retention_refcnt;
7272

73+
/* pin banks of exynos2200 pin-controller - ALIVE */
74+
static const struct samsung_pin_bank_data exynos2200_pin_banks0[] __initconst = {
75+
EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00),
76+
EXYNOS850_PIN_BANK_EINTW(8, 0x20, "gpa1", 0x04),
77+
EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa2", 0x08),
78+
EXYNOS850_PIN_BANK_EINTW(8, 0x60, "gpa3", 0x0c),
79+
EXYNOS850_PIN_BANK_EINTW(2, 0x80, "gpa4", 0x10),
80+
EXYNOS_PIN_BANK_EINTN(4, 0xa0, "gpq0"),
81+
EXYNOS_PIN_BANK_EINTN(2, 0xc0, "gpq1"),
82+
EXYNOS_PIN_BANK_EINTN(2, 0xe0, "gpq2"),
83+
};
84+
85+
/* pin banks of exynos2200 pin-controller - CMGP */
86+
static const struct samsung_pin_bank_data exynos2200_pin_banks1[] __initconst = {
87+
EXYNOS850_PIN_BANK_EINTW(2, 0x0, "gpm0", 0x00),
88+
EXYNOS850_PIN_BANK_EINTW(2, 0x20, "gpm1", 0x04),
89+
EXYNOS850_PIN_BANK_EINTW(2, 0x40, "gpm2", 0x08),
90+
EXYNOS850_PIN_BANK_EINTW(2, 0x60, "gpm3", 0x0c),
91+
EXYNOS850_PIN_BANK_EINTW(2, 0x80, "gpm4", 0x10),
92+
EXYNOS850_PIN_BANK_EINTW(2, 0xa0, "gpm5", 0x14),
93+
EXYNOS850_PIN_BANK_EINTW(2, 0xc0, "gpm6", 0x18),
94+
EXYNOS850_PIN_BANK_EINTW(2, 0xe0, "gpm7", 0x1c),
95+
EXYNOS850_PIN_BANK_EINTW(2, 0x100, "gpm8", 0x20),
96+
EXYNOS850_PIN_BANK_EINTW(2, 0x120, "gpm9", 0x24),
97+
EXYNOS850_PIN_BANK_EINTW(2, 0x140, "gpm10", 0x28),
98+
EXYNOS850_PIN_BANK_EINTW(2, 0x160, "gpm11", 0x2c),
99+
EXYNOS850_PIN_BANK_EINTW(2, 0x180, "gpm12", 0x30),
100+
EXYNOS850_PIN_BANK_EINTW(2, 0x1a0, "gpm13", 0x34),
101+
EXYNOS850_PIN_BANK_EINTW(1, 0x1c0, "gpm14", 0x38),
102+
EXYNOS850_PIN_BANK_EINTW(1, 0x1e0, "gpm15", 0x3c),
103+
EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40),
104+
EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44),
105+
EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm20", 0x48),
106+
EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm21", 0x4c),
107+
EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm22", 0x50),
108+
EXYNOS850_PIN_BANK_EINTW(1, 0x2a0, "gpm23", 0x54),
109+
EXYNOS850_PIN_BANK_EINTW(1, 0x2c0, "gpm24", 0x58),
110+
};
111+
112+
/* pin banks of exynos2200 pin-controller - HSI1 */
113+
static const struct samsung_pin_bank_data exynos2200_pin_banks2[] __initconst = {
114+
EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpf0", 0x00),
115+
};
116+
117+
/* pin banks of exynos2200 pin-controller - UFS */
118+
static const struct samsung_pin_bank_data exynos2200_pin_banks3[] __initconst = {
119+
EXYNOS850_PIN_BANK_EINTG(7, 0x0, "gpf1", 0x00),
120+
};
121+
122+
/* pin banks of exynos2200 pin-controller - HSI1UFS */
123+
static const struct samsung_pin_bank_data exynos2200_pin_banks4[] __initconst = {
124+
EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gpf2", 0x00),
125+
};
126+
127+
/* pin banks of exynos2200 pin-controller - PERIC0 */
128+
static const struct samsung_pin_bank_data exynos2200_pin_banks5[] __initconst = {
129+
EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpb0", 0x00),
130+
EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpb1", 0x04),
131+
EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpb2", 0x08),
132+
EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpb3", 0x0c),
133+
EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10),
134+
EXYNOS850_PIN_BANK_EINTG(2, 0xa0, "gpc0", 0x14),
135+
EXYNOS850_PIN_BANK_EINTG(2, 0xc0, "gpc1", 0x18),
136+
EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpc2", 0x1c),
137+
EXYNOS850_PIN_BANK_EINTG(7, 0x100, "gpg1", 0x20),
138+
EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpg2", 0x24),
139+
};
140+
141+
/* pin banks of exynos2200 pin-controller - PERIC1 */
142+
static const struct samsung_pin_bank_data exynos2200_pin_banks6[] __initconst = {
143+
EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpp7", 0x00),
144+
EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp8", 0x04),
145+
EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp9", 0x08),
146+
EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpp10", 0x0c),
147+
};
148+
149+
/* pin banks of exynos2200 pin-controller - PERIC2 */
150+
static const struct samsung_pin_bank_data exynos2200_pin_banks7[] __initconst = {
151+
EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpp0", 0x00),
152+
EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04),
153+
EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08),
154+
EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpp3", 0x0c),
155+
EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp5", 0x10),
156+
EXYNOS850_PIN_BANK_EINTG(4, 0xa0, "gpp6", 0x14),
157+
EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpp11", 0x18),
158+
EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpc3", 0x1c),
159+
EXYNOS850_PIN_BANK_EINTG(2, 0x100, "gpc4", 0x20),
160+
EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpc5", 0x24),
161+
EXYNOS850_PIN_BANK_EINTG(2, 0x140, "gpc6", 0x28),
162+
EXYNOS850_PIN_BANK_EINTG(2, 0x160, "gpc7", 0x2c),
163+
EXYNOS850_PIN_BANK_EINTG(2, 0x180, "gpc8", 0x30),
164+
EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpc9", 0x34),
165+
EXYNOS850_PIN_BANK_EINTG(5, 0x1c0, "gpg0", 0x38),
166+
};
167+
168+
/* pin banks of exynos2200 pin-controller - VTS */
169+
static const struct samsung_pin_bank_data exynos2200_pin_banks8[] __initconst = {
170+
EXYNOS850_PIN_BANK_EINTG(7, 0x0, "gpv0", 0x00),
171+
};
172+
173+
static const struct samsung_pin_ctrl exynos2200_pin_ctrl[] = {
174+
{
175+
/* pin-controller instance 0 ALIVE data */
176+
.pin_banks = exynos2200_pin_banks0,
177+
.nr_banks = ARRAY_SIZE(exynos2200_pin_banks0),
178+
.eint_gpio_init = exynos_eint_gpio_init,
179+
.eint_wkup_init = exynos_eint_wkup_init,
180+
.suspend = exynos_pinctrl_suspend,
181+
.resume = exynos_pinctrl_resume,
182+
}, {
183+
/* pin-controller instance 1 CMGP data */
184+
.pin_banks = exynos2200_pin_banks1,
185+
.nr_banks = ARRAY_SIZE(exynos2200_pin_banks1),
186+
.eint_gpio_init = exynos_eint_gpio_init,
187+
.eint_wkup_init = exynos_eint_wkup_init,
188+
.suspend = exynos_pinctrl_suspend,
189+
.resume = exynos_pinctrl_resume,
190+
}, {
191+
/* pin-controller instance 2 HSI1 data */
192+
.pin_banks = exynos2200_pin_banks2,
193+
.nr_banks = ARRAY_SIZE(exynos2200_pin_banks2),
194+
}, {
195+
/* pin-controller instance 3 UFS data */
196+
.pin_banks = exynos2200_pin_banks3,
197+
.nr_banks = ARRAY_SIZE(exynos2200_pin_banks3),
198+
.eint_gpio_init = exynos_eint_gpio_init,
199+
.suspend = exynos_pinctrl_suspend,
200+
.resume = exynos_pinctrl_resume,
201+
}, {
202+
/* pin-controller instance 4 HSI1UFS data */
203+
.pin_banks = exynos2200_pin_banks4,
204+
.nr_banks = ARRAY_SIZE(exynos2200_pin_banks4),
205+
.eint_gpio_init = exynos_eint_gpio_init,
206+
.suspend = exynos_pinctrl_suspend,
207+
.resume = exynos_pinctrl_resume,
208+
}, {
209+
/* pin-controller instance 5 PERIC0 data */
210+
.pin_banks = exynos2200_pin_banks5,
211+
.nr_banks = ARRAY_SIZE(exynos2200_pin_banks5),
212+
.eint_gpio_init = exynos_eint_gpio_init,
213+
.suspend = exynos_pinctrl_suspend,
214+
.resume = exynos_pinctrl_resume,
215+
}, {
216+
/* pin-controller instance 6 PERIC1 data */
217+
.pin_banks = exynos2200_pin_banks6,
218+
.nr_banks = ARRAY_SIZE(exynos2200_pin_banks6),
219+
.eint_gpio_init = exynos_eint_gpio_init,
220+
.suspend = exynos_pinctrl_suspend,
221+
.resume = exynos_pinctrl_resume,
222+
}, {
223+
/* pin-controller instance 7 PERIC2 data */
224+
.pin_banks = exynos2200_pin_banks7,
225+
.nr_banks = ARRAY_SIZE(exynos2200_pin_banks7),
226+
.eint_gpio_init = exynos_eint_gpio_init,
227+
.suspend = exynos_pinctrl_suspend,
228+
.resume = exynos_pinctrl_resume,
229+
}, {
230+
/* pin-controller instance 8 VTS data */
231+
.pin_banks = exynos2200_pin_banks8,
232+
.nr_banks = ARRAY_SIZE(exynos2200_pin_banks8),
233+
},
234+
};
235+
236+
const struct samsung_pinctrl_of_match_data exynos2200_of_data __initconst = {
237+
.ctrl = exynos2200_pin_ctrl,
238+
.num_ctrl = ARRAY_SIZE(exynos2200_pin_ctrl),
239+
};
240+
73241
/* pin banks of exynos5433 pin-controller - ALIVE */
74242
static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = {
75243
/* Must start with EINTG banks, ordered by EINT group number. */

‎drivers/pinctrl/samsung/pinctrl-samsung.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1469,6 +1469,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
14691469
#ifdef CONFIG_PINCTRL_EXYNOS_ARM64
14701470
{ .compatible = "google,gs101-pinctrl",
14711471
.data = &gs101_of_data },
1472+
{ .compatible = "samsung,exynos2200-pinctrl",
1473+
.data = &exynos2200_of_data },
14721474
{ .compatible = "samsung,exynos5433-pinctrl",
14731475
.data = &exynos5433_of_data },
14741476
{ .compatible = "samsung,exynos7-pinctrl",

‎drivers/pinctrl/samsung/pinctrl-samsung.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -373,6 +373,7 @@ struct samsung_pmx_func {
373373
};
374374

375375
/* list of all exported SoC specific data */
376+
extern const struct samsung_pinctrl_of_match_data exynos2200_of_data;
376377
extern const struct samsung_pinctrl_of_match_data exynos3250_of_data;
377378
extern const struct samsung_pinctrl_of_match_data exynos4210_of_data;
378379
extern const struct samsung_pinctrl_of_match_data exynos4x12_of_data;

0 commit comments

Comments
 (0)