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Sam ProtsenkoSylwester Nawrocki
Sam Protsenko
authored and
Sylwester Nawrocki
committed
clk: samsung: exynos850: Implement CMU_APM domain
CMU_APM clock domain provides clocks for APM IP-core (Active Power Management). According to Exynos850 TRM, CMU_APM generates I3C, Mailbox, Speedy, Timer, WDT, RTC and PMU clocks for BLK_ALIVE. This patch adds next clocks: - bus clocks in CMU_TOP needed for CMU_APM - all internal CMU_APM clocks - leaf clocks for I3C, Speedy and RTC IP-cores - bus clocks for CMU_CMGP and CMU_CHUB CMU_APM doesn't belong to Power Domains, but platform driver is used for its registration to keep its bus clock always running. Otherwise rtc-s3c driver disables that clock and system freezes. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20211121232741.6967-3-semen.protsenko@linaro.org
1 parent 16e0c24 commit 579839a

1 file changed

Lines changed: 141 additions & 1 deletion

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‎drivers/clk/samsung/clk-exynos850.c‎

Lines changed: 141 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,7 @@ static void __init exynos850_init_clocks(struct device_node *np,
7272
#define PLL_CON3_PLL_SHARED0 0x014c
7373
#define PLL_CON0_PLL_SHARED1 0x0180
7474
#define PLL_CON3_PLL_SHARED1 0x018c
75+
#define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000
7576
#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
7677
#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
7778
#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
@@ -83,6 +84,7 @@ static void __init exynos850_init_clocks(struct device_node *np,
8384
#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
8485
#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
8586
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
87+
#define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c
8688
#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820
8789
#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
8890
#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
@@ -100,6 +102,7 @@ static void __init exynos850_init_clocks(struct device_node *np,
100102
#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898
101103
#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
102104
#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
105+
#define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
103106
#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
104107
#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
105108
#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
@@ -122,6 +125,7 @@ static const unsigned long top_clk_regs[] __initconst = {
122125
PLL_CON3_PLL_SHARED0,
123126
PLL_CON0_PLL_SHARED1,
124127
PLL_CON3_PLL_SHARED1,
128+
CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
125129
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
126130
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
127131
CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
@@ -133,6 +137,7 @@ static const unsigned long top_clk_regs[] __initconst = {
133137
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
134138
CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
135139
CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
140+
CLK_CON_DIV_CLKCMU_APM_BUS,
136141
CLK_CON_DIV_CLKCMU_CORE_BUS,
137142
CLK_CON_DIV_CLKCMU_CORE_CCI,
138143
CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
@@ -150,6 +155,7 @@ static const unsigned long top_clk_regs[] __initconst = {
150155
CLK_CON_DIV_PLL_SHARED1_DIV2,
151156
CLK_CON_DIV_PLL_SHARED1_DIV3,
152157
CLK_CON_DIV_PLL_SHARED1_DIV4,
158+
CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
153159
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
154160
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
155161
CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
@@ -183,6 +189,8 @@ static const struct samsung_pll_clock top_pll_clks[] __initconst = {
183189
PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
184190
PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
185191
PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
192+
/* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */
193+
PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" };
186194
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
187195
PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3",
188196
"dout_shared1_div3", "dout_shared0_div4" };
@@ -222,6 +230,10 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
222230
MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
223231
PLL_CON0_PLL_MMC, 4, 1),
224232

233+
/* APM */
234+
MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus",
235+
mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
236+
225237
/* CORE */
226238
MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
227239
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
@@ -268,6 +280,10 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
268280
DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
269281
CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
270282

283+
/* APM */
284+
DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus",
285+
"gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
286+
271287
/* CORE */
272288
DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
273289
CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
@@ -310,6 +326,10 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
310326
GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss",
311327
CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0),
312328

329+
/* APM */
330+
GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus",
331+
"mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
332+
313333
/* DPU */
314334
GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
315335
CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
@@ -354,6 +374,124 @@ static void __init exynos850_cmu_top_init(struct device_node *np)
354374
CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top",
355375
exynos850_cmu_top_init);
356376

377+
/* ---- CMU_APM ------------------------------------------------------------- */
378+
379+
/* Register Offset definitions for CMU_APM (0x11800000) */
380+
#define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600
381+
#define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610
382+
#define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620
383+
#define PLL_CON0_MUX_DLL_USER 0x0630
384+
#define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000
385+
#define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004
386+
#define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008
387+
#define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800
388+
#define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804
389+
#define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808
390+
#define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000
391+
#define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014
392+
#define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024
393+
#define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028
394+
#define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034
395+
#define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038
396+
#define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc
397+
398+
static const unsigned long apm_clk_regs[] __initconst = {
399+
PLL_CON0_MUX_CLKCMU_APM_BUS_USER,
400+
PLL_CON0_MUX_CLK_RCO_APM_I3C_USER,
401+
PLL_CON0_MUX_CLK_RCO_APM_USER,
402+
PLL_CON0_MUX_DLL_USER,
403+
CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS,
404+
CLK_CON_MUX_MUX_CLK_APM_BUS,
405+
CLK_CON_MUX_MUX_CLK_APM_I3C,
406+
CLK_CON_DIV_CLKCMU_CHUB_BUS,
407+
CLK_CON_DIV_DIV_CLK_APM_BUS,
408+
CLK_CON_DIV_DIV_CLK_APM_I3C,
409+
CLK_CON_GAT_CLKCMU_CMGP_BUS,
410+
CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS,
411+
CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK,
412+
CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK,
413+
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK,
414+
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK,
415+
CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK,
416+
};
417+
418+
/* List of parent clocks for Muxes in CMU_APM */
419+
PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" };
420+
PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" };
421+
PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" };
422+
PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" };
423+
PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" };
424+
PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user",
425+
"mout_dll_user", "oscclk_rco_apm" };
426+
PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" };
427+
428+
static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
429+
FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000),
430+
FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000),
431+
FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000),
432+
FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000),
433+
};
434+
435+
static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
436+
MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p,
437+
PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1),
438+
MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user",
439+
mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1),
440+
MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p,
441+
PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1),
442+
MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p,
443+
PLL_CON0_MUX_DLL_USER, 4, 1),
444+
MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus",
445+
mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1),
446+
MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p,
447+
CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2),
448+
MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p,
449+
CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1),
450+
};
451+
452+
static const struct samsung_div_clock apm_div_clks[] __initconst = {
453+
DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus",
454+
"gout_clkcmu_chub_bus",
455+
CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3),
456+
DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus",
457+
CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3),
458+
DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus",
459+
CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3),
460+
};
461+
462+
static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
463+
GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus",
464+
CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0),
465+
GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus",
466+
"mout_clkcmu_chub_bus",
467+
CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0),
468+
GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus",
469+
CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0),
470+
GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus",
471+
CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0),
472+
GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus",
473+
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0),
474+
GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c",
475+
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0),
476+
GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus",
477+
CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0),
478+
};
479+
480+
static const struct samsung_cmu_info apm_cmu_info __initconst = {
481+
.mux_clks = apm_mux_clks,
482+
.nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
483+
.div_clks = apm_div_clks,
484+
.nr_div_clks = ARRAY_SIZE(apm_div_clks),
485+
.gate_clks = apm_gate_clks,
486+
.nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
487+
.fixed_clks = apm_fixed_clks,
488+
.nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
489+
.nr_clk_ids = APM_NR_CLK,
490+
.clk_regs = apm_clk_regs,
491+
.nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
492+
.clk_name = "dout_clkcmu_apm_bus",
493+
};
494+
357495
/* ---- CMU_HSI ------------------------------------------------------------- */
358496

359497
/* Register Offset definitions for CMU_HSI (0x13400000) */
@@ -801,9 +939,11 @@ static int __init exynos850_cmu_probe(struct platform_device *pdev)
801939
return 0;
802940
}
803941

804-
/* CMUs which belong to Power Domains and need runtime PM to be implemented */
805942
static const struct of_device_id exynos850_cmu_of_match[] = {
806943
{
944+
.compatible = "samsung,exynos850-cmu-apm",
945+
.data = &apm_cmu_info,
946+
}, {
807947
.compatible = "samsung,exynos850-cmu-hsi",
808948
.data = &hsi_cmu_info,
809949
}, {

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