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drm/msm: Update generated headers
Update headers from mesa commit: commit 7e63fa2bb13cf14b765ad06d046789ee1879b5ef Author: Rob Clark <robclark@freedesktop.org> AuthorDate: Wed Mar 2 17:11:10 2022 -0800 freedreno/registers: Add a couple regs we need for kernel Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15221> Signed-off-by: Rob Clark <robdclark@chromium.org> [for display bits:] Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Link: https://lore.kernel.org/r/20220304005317.776110-2-robdclark@gmail.com
1 parent 8ddb80c commit 57cfe41

23 files changed

Lines changed: 894 additions & 1118 deletions

‎drivers/gpu/drm/msm/adreno/a2xx.xml.h‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
88
git clone https://github.com/freedreno/envytools.git
99
1010
The rules-ng-ng source files this header was generated from are:
11-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
11+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22)
12+
- /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32)
13+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24)
14+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10)
15+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33)
16+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10)
17+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21)
18+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21)
19+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33)
20+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56)
21+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22)
22+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56)
23+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56)
2424
2525
Copyright (C) 2013-2021 by the following authors:
2626
- Rob Clark <robdclark@gmail.com> (robclark)

‎drivers/gpu/drm/msm/adreno/a3xx.xml.h‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
88
git clone https://github.com/freedreno/envytools.git
99
1010
The rules-ng-ng source files this header was generated from are:
11-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
11+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22)
12+
- /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32)
13+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24)
14+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10)
15+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33)
16+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10)
17+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21)
18+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21)
19+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33)
20+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56)
21+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22)
22+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56)
23+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56)
2424
2525
Copyright (C) 2013-2021 by the following authors:
2626
- Rob Clark <robdclark@gmail.com> (robclark)
@@ -1466,7 +1466,7 @@ static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endi
14661466

14671467
#define REG_A3XX_RB_DEPTH_CONTROL 0x00002100
14681468
#define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
1469-
#define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
1469+
#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x00000002
14701470
#define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
14711471
#define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008
14721472
#define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
@@ -1476,7 +1476,7 @@ static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
14761476
return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
14771477
}
14781478
#define A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080
1479-
#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
1479+
#define A3XX_RB_DEPTH_CONTROL_Z_READ_ENABLE 0x80000000
14801480

14811481
#define REG_A3XX_RB_DEPTH_CLEAR 0x00002101
14821482

‎drivers/gpu/drm/msm/adreno/a4xx.xml.h‎

Lines changed: 93 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -8,21 +8,21 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
88
git clone https://github.com/freedreno/envytools.git
99
1010
The rules-ng-ng source files this header was generated from are:
11-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24-
25-
Copyright (C) 2013-2021 by the following authors:
11+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22)
12+
- /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32)
13+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24)
14+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10)
15+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33)
16+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10)
17+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21)
18+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21)
19+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33)
20+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56)
21+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22)
22+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56)
23+
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56)
24+
25+
Copyright (C) 2013-2022 by the following authors:
2626
- Rob Clark <robdclark@gmail.com> (robclark)
2727
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
2828
@@ -837,6 +837,7 @@ enum a4xx_tex_type {
837837
A4XX_TEX_2D = 1,
838838
A4XX_TEX_CUBE = 2,
839839
A4XX_TEX_3D = 3,
840+
A4XX_TEX_BUFFER = 4,
840841
};
841842

842843
#define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000
@@ -1360,7 +1361,7 @@ static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
13601361

13611362
#define REG_A4XX_RB_DEPTH_CONTROL 0x00002101
13621363
#define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
1363-
#define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
1364+
#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x00000002
13641365
#define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
13651366
#define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
13661367
#define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
@@ -1371,7 +1372,7 @@ static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
13711372
#define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080
13721373
#define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
13731374
#define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000
1374-
#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
1375+
#define A4XX_RB_DEPTH_CONTROL_Z_READ_ENABLE 0x80000000
13751376

13761377
#define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
13771378

@@ -2541,6 +2542,8 @@ static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
25412542
return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK;
25422543
}
25432544
#define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
2545+
#define A4XX_SP_FS_MRT_REG_COLOR_SINT 0x00000400
2546+
#define A4XX_SP_FS_MRT_REG_COLOR_UINT 0x00000800
25442547
#define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000
25452548
#define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12
25462549
static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
@@ -2550,6 +2553,40 @@ static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
25502553
#define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000
25512554

25522555
#define REG_A4XX_SP_CS_CTRL_REG0 0x00002300
2556+
#define A4XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001
2557+
#define A4XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0
2558+
static inline uint32_t A4XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2559+
{
2560+
return ((val) << A4XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_CS_CTRL_REG0_THREADMODE__MASK;
2561+
}
2562+
#define A4XX_SP_CS_CTRL_REG0_VARYING 0x00000002
2563+
#define A4XX_SP_CS_CTRL_REG0_CACHEINVALID 0x00000004
2564+
#define A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2565+
#define A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
2566+
static inline uint32_t A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2567+
{
2568+
return ((val) << A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2569+
}
2570+
#define A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
2571+
#define A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2572+
static inline uint32_t A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2573+
{
2574+
return ((val) << A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2575+
}
2576+
#define A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
2577+
#define A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
2578+
static inline uint32_t A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
2579+
{
2580+
return ((val) << A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__MASK;
2581+
}
2582+
#define A4XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2583+
#define A4XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
2584+
static inline uint32_t A4XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2585+
{
2586+
return ((val) << A4XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
2587+
}
2588+
#define A4XX_SP_CS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2589+
#define A4XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00400000
25532590

25542591
#define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301
25552592

@@ -3795,12 +3832,18 @@ static inline uint32_t A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val)
37953832
#define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3
37963833

37973834
#define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4
3798-
#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK 0x000000ff
3835+
#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK 0x00000fff
37993836
#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT 0
38003837
static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val)
38013838
{
38023839
return ((val) << A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK;
38033840
}
3841+
#define A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__MASK 0x00fff000
3842+
#define A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__SHIFT 12
3843+
static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID(uint32_t val)
3844+
{
3845+
return ((val) << A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__MASK;
3846+
}
38043847
#define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK 0xff000000
38053848
#define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT 24
38063849
static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val)
@@ -3809,8 +3852,32 @@ static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val)
38093852
}
38103853

38113854
#define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5
3855+
#define A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__MASK 0x00000fff
3856+
#define A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__SHIFT 0
3857+
static inline uint32_t A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID(uint32_t val)
3858+
{
3859+
return ((val) << A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__MASK;
3860+
}
3861+
#define A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__MASK 0x00fff000
3862+
#define A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__SHIFT 12
3863+
static inline uint32_t A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID(uint32_t val)
3864+
{
3865+
return ((val) << A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__MASK;
3866+
}
38123867

38133868
#define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6
3869+
#define A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__MASK 0x00000fff
3870+
#define A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__SHIFT 0
3871+
static inline uint32_t A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID(uint32_t val)
3872+
{
3873+
return ((val) << A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__SHIFT) & A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__MASK;
3874+
}
3875+
#define A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__MASK 0x00fff000
3876+
#define A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__SHIFT 12
3877+
static inline uint32_t A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID(uint32_t val)
3878+
{
3879+
return ((val) << A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__SHIFT) & A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__MASK;
3880+
}
38143881

38153882
#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7
38163883

@@ -3819,6 +3886,12 @@ static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val)
38193886
#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9
38203887

38213888
#define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da
3889+
#define A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__MASK 0x00000fff
3890+
#define A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__SHIFT 0
3891+
static inline uint32_t A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID(uint32_t val)
3892+
{
3893+
return ((val) << A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__SHIFT) & A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__MASK;
3894+
}
38223895

38233896
#define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db
38243897

@@ -4130,7 +4203,7 @@ static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
41304203
{
41314204
return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK;
41324205
}
4133-
#define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000
4206+
#define A4XX_TEX_CONST_0_TYPE__MASK 0xe0000000
41344207
#define A4XX_TEX_CONST_0_TYPE__SHIFT 29
41354208
static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
41364209
{
@@ -4158,6 +4231,7 @@ static inline uint32_t A4XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
41584231
{
41594232
return ((val) << A4XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A4XX_TEX_CONST_2_PITCHALIGN__MASK;
41604233
}
4234+
#define A4XX_TEX_CONST_2_BUFFER 0x00000040
41614235
#define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00
41624236
#define A4XX_TEX_CONST_2_PITCH__SHIFT 9
41634237
static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)

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