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davejiang
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cxl/port: Export cxl_dvsec_rr_decode() to cxl_port
Call cxl_dvsec_rr_decode() in the beginning of cxl_port_probe() and preserve the decoded information in a local 'struct cxl_endpoint_dvsec_info'. This info can be passed to various functions later on in order to support the HDM decoder emulation. The invocation of cxl_dvsec_rr_decode() in cxl_hdm_decode_init() is removed and a pointer to the 'struct cxl_endpoint_dvsec_info' is passed in. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/167640367377.935665.2848747799651019676.stgit@dwillia2-xfh.jf.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
1 parent 1acba6e commit 59c3368

7 files changed

Lines changed: 56 additions & 33 deletions

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‎drivers/cxl/core/pci.c‎

Lines changed: 7 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -333,8 +333,8 @@ static bool __cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
333333
return true;
334334
}
335335

336-
static int cxl_dvsec_rr_decode(struct device *dev, int d,
337-
struct cxl_endpoint_dvsec_info *info)
336+
int cxl_dvsec_rr_decode(struct device *dev, int d,
337+
struct cxl_endpoint_dvsec_info *info)
338338
{
339339
struct pci_dev *pdev = to_pci_dev(dev);
340340
int hdm_count, rc, i, ranges = 0;
@@ -434,30 +434,26 @@ static int cxl_dvsec_rr_decode(struct device *dev, int d,
434434

435435
return 0;
436436
}
437+
EXPORT_SYMBOL_NS_GPL(cxl_dvsec_rr_decode, CXL);
437438

438439
/**
439440
* cxl_hdm_decode_init() - Setup HDM decoding for the endpoint
440441
* @cxlds: Device state
441442
* @cxlhdm: Mapped HDM decoder Capability
443+
* @info: Cached DVSEC range registers info
442444
*
443445
* Try to enable the endpoint's HDM Decoder Capability
444446
*/
445-
int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm)
447+
int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
448+
struct cxl_endpoint_dvsec_info *info)
446449
{
447-
struct cxl_endpoint_dvsec_info info = { 0 };
448450
struct device *dev = cxlds->dev;
449-
int d = cxlds->cxl_dvsec;
450-
int rc;
451-
452-
rc = cxl_dvsec_rr_decode(dev, d, &info);
453-
if (rc < 0)
454-
return rc;
455451

456452
/*
457453
* If DVSEC ranges are being used instead of HDM decoder registers there
458454
* is no use in trying to manage those.
459455
*/
460-
if (!__cxl_hdm_decode_init(cxlds, cxlhdm, &info)) {
456+
if (!__cxl_hdm_decode_init(cxlds, cxlhdm, info)) {
461457
dev_err(dev,
462458
"Legacy range registers configuration prevents HDM operation.\n");
463459
return -EBUSY;

‎drivers/cxl/cxl.h‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -630,10 +630,24 @@ int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map);
630630
int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld);
631631
int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint);
632632

633+
/**
634+
* struct cxl_endpoint_dvsec_info - Cached DVSEC info
635+
* @mem_enabled: cached value of mem_enabled in the DVSEC, PCIE_DEVICE
636+
* @ranges: Number of active HDM ranges this device uses.
637+
* @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE
638+
*/
639+
struct cxl_endpoint_dvsec_info {
640+
bool mem_enabled;
641+
int ranges;
642+
struct range dvsec_range[2];
643+
};
644+
633645
struct cxl_hdm;
634646
struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port);
635647
int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm);
636648
int devm_cxl_add_passthrough_decoder(struct cxl_port *port);
649+
int cxl_dvsec_rr_decode(struct device *dev, int dvsec,
650+
struct cxl_endpoint_dvsec_info *info);
637651

638652
bool is_cxl_region(struct device *dev);
639653

‎drivers/cxl/cxlmem.h‎

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -181,18 +181,6 @@ static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd)
181181
*/
182182
#define CXL_CAPACITY_MULTIPLIER SZ_256M
183183

184-
/**
185-
* struct cxl_endpoint_dvsec_info - Cached DVSEC info
186-
* @mem_enabled: cached value of mem_enabled in the DVSEC, PCIE_DEVICE
187-
* @ranges: Number of active HDM ranges this device uses.
188-
* @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE
189-
*/
190-
struct cxl_endpoint_dvsec_info {
191-
bool mem_enabled;
192-
int ranges;
193-
struct range dvsec_range[2];
194-
};
195-
196184
/**
197185
* struct cxl_dev_state - The driver device state
198186
*

‎drivers/cxl/cxlpci.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -64,6 +64,7 @@ enum cxl_regloc_type {
6464

6565
int devm_cxl_port_enumerate_dports(struct cxl_port *port);
6666
struct cxl_dev_state;
67-
int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm);
67+
int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
68+
struct cxl_endpoint_dvsec_info *info);
6869
void read_cdat_data(struct cxl_port *port);
6970
#endif /* __CXL_PCI_H__ */

‎drivers/cxl/port.c‎

Lines changed: 13 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -32,12 +32,21 @@ static void schedule_detach(void *cxlmd)
3232

3333
static int cxl_port_probe(struct device *dev)
3434
{
35+
struct cxl_endpoint_dvsec_info info = { 0 };
3536
struct cxl_port *port = to_cxl_port(dev);
37+
bool is_ep = is_cxl_endpoint(port);
38+
struct cxl_dev_state *cxlds;
39+
struct cxl_memdev *cxlmd;
3640
struct cxl_hdm *cxlhdm;
3741
int rc;
3842

39-
40-
if (!is_cxl_endpoint(port)) {
43+
if (is_ep) {
44+
cxlmd = to_cxl_memdev(port->uport);
45+
cxlds = cxlmd->cxlds;
46+
rc = cxl_dvsec_rr_decode(cxlds->dev, cxlds->cxl_dvsec, &info);
47+
if (rc < 0)
48+
return rc;
49+
} else {
4150
rc = devm_cxl_port_enumerate_dports(port);
4251
if (rc < 0)
4352
return rc;
@@ -49,10 +58,7 @@ static int cxl_port_probe(struct device *dev)
4958
if (IS_ERR(cxlhdm))
5059
return PTR_ERR(cxlhdm);
5160

52-
if (is_cxl_endpoint(port)) {
53-
struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport);
54-
struct cxl_dev_state *cxlds = cxlmd->cxlds;
55-
61+
if (is_ep) {
5662
/* Cache the data early to ensure is_visible() works */
5763
read_cdat_data(port);
5864

@@ -61,7 +67,7 @@ static int cxl_port_probe(struct device *dev)
6167
if (rc)
6268
return rc;
6369

64-
rc = cxl_hdm_decode_init(cxlds, cxlhdm);
70+
rc = cxl_hdm_decode_init(cxlds, cxlhdm, &info);
6571
if (rc)
6672
return rc;
6773

‎tools/testing/cxl/Kbuild‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ ldflags-y += --wrap=devm_cxl_add_passthrough_decoder
1010
ldflags-y += --wrap=devm_cxl_enumerate_decoders
1111
ldflags-y += --wrap=cxl_await_media_ready
1212
ldflags-y += --wrap=cxl_hdm_decode_init
13+
ldflags-y += --wrap=cxl_dvsec_rr_decode
1314
ldflags-y += --wrap=cxl_rcrb_to_component
1415

1516
DRIVERS := ../../../drivers

‎tools/testing/cxl/test/mock.c‎

Lines changed: 19 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -209,21 +209,38 @@ int __wrap_cxl_await_media_ready(struct cxl_dev_state *cxlds)
209209
EXPORT_SYMBOL_NS_GPL(__wrap_cxl_await_media_ready, CXL);
210210

211211
int __wrap_cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
212-
struct cxl_hdm *cxlhdm)
212+
struct cxl_hdm *cxlhdm,
213+
struct cxl_endpoint_dvsec_info *info)
213214
{
214215
int rc = 0, index;
215216
struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
216217

217218
if (ops && ops->is_mock_dev(cxlds->dev))
218219
rc = 0;
219220
else
220-
rc = cxl_hdm_decode_init(cxlds, cxlhdm);
221+
rc = cxl_hdm_decode_init(cxlds, cxlhdm, info);
221222
put_cxl_mock_ops(index);
222223

223224
return rc;
224225
}
225226
EXPORT_SYMBOL_NS_GPL(__wrap_cxl_hdm_decode_init, CXL);
226227

228+
int __wrap_cxl_dvsec_rr_decode(struct device *dev, int dvsec,
229+
struct cxl_endpoint_dvsec_info *info)
230+
{
231+
int rc = 0, index;
232+
struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
233+
234+
if (ops && ops->is_mock_dev(dev))
235+
rc = 0;
236+
else
237+
rc = cxl_dvsec_rr_decode(dev, dvsec, info);
238+
put_cxl_mock_ops(index);
239+
240+
return rc;
241+
}
242+
EXPORT_SYMBOL_NS_GPL(__wrap_cxl_dvsec_rr_decode, CXL);
243+
227244
resource_size_t __wrap_cxl_rcrb_to_component(struct device *dev,
228245
resource_size_t rcrb,
229246
enum cxl_rcrb which)

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